AD9627-11 Analog Devices, AD9627-11 Datasheet - Page 7

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AD9627-11

Manufacturer Part Number
AD9627-11
Description
11-Bit, 105 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9627-11

Resolution (bits)
11bit
# Chan
2
Sample Rate
150MSPS
Interface
Par
Analog Input Type
Diff-Uni
Ain Range
(2Vref) p-p,1 V p-p,2 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and
DCS enabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
SYNC INPUT
LOGIC INPUT (CSB)
LOGIC INPUT (SCLK/DFS)
LOGIC INPUTS/OUTPUTS (SDIO/DCS, SMI SDFS)
LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 3.3 V)
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 3.3 V)
Low Level Input Current
1
2
1
2
Rev. B | Page 7 of 72
Full
Full
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
0.2
GND − 0.3
1.1
1.2
0
−10
−10
8
GND − 0.3
1.2
0
−10
−10
8
1.22
0
−10
40
1.22
0
−92
−10
1.22
0
−10
38
1.22
0
−90
−10
CMOS/LVDS/LVPECL
Typ
1.2
4
10
CMOS
1.2
4
10
26
2
26
2
26
5
Max
6
AVDD + 1.6
AVDD
3.6
0.8
+10
+10
12
AVDD + 1.6
3.6
0.8
+10
+10
12
3.6
0.6
+10
132
3.6
0.6
−135
+10
3.6
0.6
+10
128
3.6
0.6
−134
+10
AD9627-11
Unit
V
V p-p
V
V
V
V
μA
μA
pF
V
V
V
V
μA
μA
pF
kΩ
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA

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