AD9627-11 Analog Devices, AD9627-11 Datasheet - Page 10

• Manufacturer Part Number: AD9627-11
• Description: 11-Bit, 105 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9627-11

• Resolution (bits): 11bit
• # Chan: 2
• Sample Rate: 150MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9627-11
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
SPORT TIMING REQUIREMENTS
Timing Diagrams
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
CSSCLK
SSCLKSDO
SSCLKSDFS
CH A/CH B DATA
CH A/CH B FAST
DCOA/DCOB
Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)
DETECT
CLK+
CLK–
Test Conditions/Comments
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
Delay from rising edge of CLK+ to rising edge of SMI SCLK
Delay from rising edge of SMI SCLK to SMI SDO
Delay from rising edge of SMI SCLK to SMI SDFS
N – 13
N – 3
N
t
S
t
t
A
PD
N – 12
N – 2
N + 1
t
CLK
t
H
N – 11
N + 2
N – 1
Rev. B | Page 10 of 72
N – 10
N + 3
N
t
DCO
N – 9
N + 1
N + 4
N – 8
N + 2
N + 5
t
CLK
N + 6
N + 3
N – 7
N + 7
N – 6
N + 4
Min
2
2
40
2
2
10
10
10
10
3.2
−0.4
−0.4
N + 8
N – 5
N + 5
N – 4
N + 6
Typ
0.24
0.40
4.5
0
0
Max
6.2
0.4
0.4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns