AD9600 Analog Devices, AD9600 Datasheet - Page 46

• Manufacturer Part Number: AD9600
• Description: 10-Bit, 105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9600

• Resolution (bits): 10bit
• # Chan: 2
• Sample Rate: 150MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9600
Signal Monitor Period (Register 0x113 to Register 0x115)
Register 0x113, Bits [7:0]—Signal Monitor Period [7:0]
Register 0x114, Bits [7:0]—Signal Monitor Period [15:8]
Register 0x115, Bits [7:0]—Signal Monitor Period [23:16]
This 24-bit value sets the number of clock cycles over which
the signal monitor performs its operation. Although this
register defaults to 64 (0x40), the minimum value for this
register is 128 (0x80) cycles—writing values less than 128
can cause inaccurate results.
Signal Monitor Result Channel A (Register 0x116 to
Register 0x118)
Register 0x116, Bits [7:0]—Signal Monitor Result
Channel A [7:0]
Register 0x117, Bits [7:0]—Signal Monitor Result
Channel A [15:8]
Register 0x118, Bits [7:4]—Reserved
Register 0x118, Bits [3:0]—Signal Monitor Result
Channel A [19:16]
This 20-bit value contains the result calculated by the signal
monitoring block for Channel A. The content is dependent on the
settings in Bits [2:1] of Register 0x112.
Rev. B | Page 46 of 72
Signal Monitor Result Channel B (Register 0x119 to
Register 0x11B)
Register 0x119, Bits [7:0]— Signal Monitor Result
Channel B [7:0]
Register 0x11A, Bits [7:0]—Signal Monitor Result
Channel B [15:8]
Register 0x11B, Bits [7:4]—Reserved
Register 0x11B, Bits [3:0]—Signal Monitor Result
Channel B [19:16]
This 20-bit value contains the result calculated by the signal
monitoring block for Channel B. The content is dependent on
the settings in Bits [2:1] of Register 0x112.