AD9600 Analog Devices, AD9600 Datasheet - Page 32

• Manufacturer Part Number: AD9600
• Description: 10-Bit, 105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9600

• Resolution (bits): 10bit
• # Chan: 2
• Sample Rate: 150MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9600
Increment Gain (IG) and Decrement Gain (DG)
The increment gain and decrement gain indicators are intended
to be used together to provide information to enable external gain
control. The decrement gain indicator works in conjunction with
the coarse upper threshold bits, asserting when the input
magnitude is greater than the 3-bit value in the coarse upper
threshold register (Address 0x105). The increment gain indicator,
similarly, corresponds with the fine lower threshold bits, except
that it is asserted only if the input magnitude is less than the
value programmed in the fine lower threshold register after the
dwell time elapses. This dwell time is set by the 16-bit increase
gain dwell time register (Address 0x10A and Address 0x10B) and
is in units of ADC input clock cycles ranging from 1 to 65,535. The
C_UT OR F_UT*
F_LT
DG
IG
*C_UT AND F_UT DIFFER ONLY IN ACCURACY AND LATENCY.
NOTE: OUTPUTS FOLLOW THE INSTANTANEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF TWO ADC CLOCK CYCLES.
Figure 66. Threshold Settings for C_UT, F_UT, F_LT, IG, and DG
RISE ABOVE F_LT
TIMER RESET BY
Rev. B | Page 32 of 72
DWELL TIME
fine lower threshold register is a 13-bit register that is compared
with the magnitude at the output of the ADC. This comparison
is subject to the ADC clock latency but allows a finer, more
accurate comparison. The fine threshold magnitude is defined
in Equation 1 (see the Fine Upper Threshold (F_UT) section).
The decrement gain output is influenced by the fast detect output
pins, which provide a fast indication of potential overrange
conditions. Assertion of the increment gain indicator is based
on the comparison at the output of the ADC, requiring the input
magnitude to remain below an accurate, programmable level for a
predefined period before signaling external circuitry to increase
the gain.
The operation of the IG and DG indicators is shown in Figure 66.
UPPER THRESHOLD (COARSE OR FINE)
DWELL TIME
FINE LOWER THRESHOLD
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE F_LT