AD7682 Analog Devices, AD7682 Datasheet - Page 30

• Manufacturer Part Number: AD7682
• Manufacturer: Analog Devices

Specifications of AD7682

• Resolution (bits): 16bit
• # Chan: 4
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Bip,SE-Uni
• Ain Range: Bip (Vref) x 0.5,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP

AD7682/AD7689
READ/WRITE SPANNING CONVERSION WITH A
BUSY INDICATOR
This mode is used when the AD7682/AD7689 are connected to
any host using an SPI, serial port, or FPGA with an interrupt
input. The connection diagram is shown in Figure 42, and the
corresponding timing is given in Figure 43. For the SPI, the
host should use CPHA = CPOL = 1. Reading/writing spanning
conversion is shown, which covers all three modes detailed in
the Digital Interface section.
A rising edge on CNV initiates a conversion, ignores data
present on DIN and forces SDO to high impedance. After the
conversion is initiated, it continues until completion irrespec-
tive of the state of CNV. CNV must be returned low before the
safe data transfer time, t
conversion time, t
When the conversion is complete, SDO transitions from high
impedance to low (data ready), and with a pull-up to VIO, SDO
can be used to interrupt the host to begin data transfer.
After the conversion is complete, the AD7682/AD7689 enter
the acquisition phase and power-down. The host must enable
the MSB of the CFG register at this time (if necessary) to begin
CONVERSION
NOTES:
1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF
CNV
16 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.
30 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.
ON THE 17TH OR 31st SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.
OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW.
SCK
SDO
DIN
(n – 1)
CONV
t
SCKH
END DATA (n – 2)
, to generate the busy signal indicator.
t
SCKL
END CFG (n)
DATA
CONVERSION (n – 1)
t
15
DATA
X
t
SCK
, and then held low beyond the
16
LSB
X
+ 1
17/
31
X
Figure 43. Serial Interface Timing for the AD7682/AD7689 with a Busy Indicator
LSB
Figure 42. Connection Diagram for the AD7682/AD7689 with a Busy Indicator
t
DIS
(QUIET
TIME)
t
UPDATE (n)
EN
t
CFG/SDO
CYC
AD7682/
AD7689
BEIGN CFG (n + 1)
FOR SPI USE CPHA = 1, CPOL = 1.
CFG
MSB
MSB
SDO
CNV
SCK
1
DIN
t
Rev. C | Page 30 of 32
SDIN
BEGIN DATA (n – 1)
MSB –1
CFG
MSB
t
– 1
HDIN
ACQUISITION (n)
2
t
ACQ
VIO
t
t
HSDO
DSDO
the CFG update. While CNV is low, both a CFG update and a
data readback take place. The first 14 SCK rising edges are used to
update the CFG register, and the first 16 SCK falling edges clock
out the conversion results starting with the MSB. The restric-
tion for both configuring and reading is that they both occur
before the t
CFG[13:0] must be written or they are ignored. Also, if the 16-bit
conversion result is not read back before t
The SDO data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 17
falling edge, SDO returns to high impedance. Note that if the
optional SCK falling edge is not used, the busy feature cannot
be detected, as described in the General Timing with a Busy
Indicator section.
If CFG readback is enabled, the CFG register associated with
the conversion result is read back MSB first following the LSB of
the conversion result. A total of 31 SCK falling edges is required
to return SDO to high impedance if this is enabled.
MISO
IRQ
SS
MOSI
SCK
DIGITAL HOST
DATA
t
t
CNVH
EN
time elapses for the next conversion. All 14 bits of
t
DIS
END DATA (n – 1)
END CFG (n + 1)
t
CONVERSION (n)
15
X
DATA
t
CONV
LSB
16
SEE NOTE
X
+ 1
SEE NOTE
17/
31
LSB
X
DATA
t
DIS
th
(QUIET
(or 31
TIME)
UPDATE (n + 1)
elapses, it is lost.
Data Sheet
t
EN
CFG/SDO
st
ACQUISITION
) SCK
(n + 1)