AD7156 Analog Devices, AD7156 Datasheet - Page 19

• Manufacturer Part Number: AD7156
• Manufacturer: Analog Devices

Specifications of AD7156

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 100SPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: Capacitive
• Ain Range: 0.5 pF,1 pF,2 pF,4 pF
• Pkg Type: CSP

SETUP REGISTERS
Ch 1 Address Pointer 0x0B
Ch 2 Address Pointer 0x0E
8 Bits, Read/Write, Factory Preset 0x0B
Table 10. Setup Registers Bit Map
1
Table 11. Setup Registers Bit Descriptions
Bit
7
6
5
4
[3:0]
The default values are given in parentheses.
RngH
Bit 7
(0)
Mnemonic
RngH
RngL
Hyst
ThrSettling
RngL
Bit 6
(0)
Description
Range bits set the CDC input range and determine the step for the auto-DAC function.
RngH
0
0
1
1
This bit should be 0 for the specified operation.
Hyst = 1 disables hysteresis in adaptive threshold mode. This bit has no effect in fixed threshold mode;
hysteresis is always disabled in the fixed threshold mode.
Determines dynamic behavior of the data average and thus the settling time of the adaptive thresholds. Data
average is calculated from the previous CDC output data, using equation:
where:
Average(N) is the new average value.
Average(N − 1) is the average value from the previous cycle.
Data(N) is the latest complete CDC conversion result.
ThrSettling is the programmable parameter.
The response of the average to an input capacitance step change (that is, response to the change in the CDC
output data) is an exponential settling curve characterized by the following equation:
where:
Average(N) is the value of average N complete CDC conversion cycles after a step change on the input.
Average(0) is the value before the step change.
TimeConst can be selected in the range between 2 and 65,536 conversion cycle multiples, in steps of power of
2, by programming the ThrSettling bits. TimeConst = 2
Average
Average
1
(
(
N
N
INPUT CAPACITANCE
)
)
(CDC DATA) CHANGE
=
=
Bit 5
Average
Average
(0)
RngL
0
1
0
1
Figure 39. Data Average Response to Data Step Change
(
(
N
) 0
−
+
) 1
Change
+
Bit 4
Hyst
Data
(0)
Rev. 0 | Page 19 of 28
Capacitive Input Range (pF)
2
0.5
1
4
1 (
(
N
−
2
)
ThrSettlin
−
e
N
Average
/ TimeConst
g
+
DATA AVERAGE RESPONSE
1
Bit 3
(
N
)
−
(ThrSettling + 1)
) 1
TIME
ThrSettling (4-Bit Value)
Bit 2
Auto-DAC Step (CAPDAC LSB)
4
1
2
8
(0x0B)
Bit 1
AD7156
Bit 0