AD7156 Analog Devices, AD7156 Datasheet - Page 11
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AD7156
Manufacturer Part Number
AD7156
Description
Manufacturer
Analog Devices
Datasheet
1.AD7156.pdf
(28 pages)
Specifications of AD7156
Resolution (bits)
12bit
# Chan
2
Sample Rate
100SPS
Interface
I²C/Ser 2-Wire,Ser
Analog Input Type
Capacitive
Ain Range
0.5 pF,1 pF,2 pF,4 pF
Pkg Type
CSP
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THEORY OF OPERATION
The AD7156 core is a high performance capacitance-to-digital
converter (CDC) that allows the part to be interfaced directly
to a capacitive sensor.
The comparators compare the CDC results with thresholds, either
fixed or dynamically adjusted by the on-chip adaptive threshold
algorithm engine. Thus, the outputs indicate a defined change in
the input sensor capacitance.
The AD7156 also integrates an excitation source, CAPDAC
for the capacitive inputs, an input multiplexer, a complete clock
generator, a power-down timer, a power supply monitor, control
logic, and an I
part and accessing the internal CDC data and status, if required
in the system (see Figure 22).
CAPACITANCE-TO-DIGITAL CONVERTER
Figure 23 shows the CDC simplified functional diagram. The
converter consists of a second-order Σ-Δ charge balancing
modulator and a third-order digital filter. The measured
capacitance C
and the Σ-Δ modulator input. The excitation signal is applied
on the C
continuously samples the charge going through the C
digital filter processes the modulator output, which is a stream
of 0s and 1s containing the information in 0 and 1 density. The
data is processed by the adaptive threshold engine and output
comparators; the data can also be read through the serial interface.
The AD7156 is designed for floating capacitive sensors.
Therefore, both C
or any other fixed potential node in the system.
The AD7156 features slew rate limiting on the excitation voltage
output, which decreases the energy of higher harmonics on the
excitation signal and dramatically improves the system electro-
magnetic compatibility (EMC).
X
capacitor during the conversion, and the modulator
X
2
C®-compatible serial interface for configuring the
is connected between an excitation source
X
plates have to be isolated from ground
C
C
X1
X2
EXC1
EXC2
CIN1
CIN2
AD7156
MUX
GENERATOR
EXCITATION
CAPDAC
CLOCK
Σ-Δ CDC
X
. The
Figure 22. AD7156 Block Diagram
Rev. 0 | Page 11 of 28
POWER-DOWN
THRESHOLD
THRESHOLD
3.3V
DIGITAL
FILTER
TIMER
GND
VDD
CAPDAC
The AD7156 CDC core maximum full-scale input range is 0 pF
to 4 pF. However, the part can accept a higher input capacitance,
caused, for example, by a nonchanging offset capacitance of up to
10 pF. This offset capacitance can be compensated for by using
the programmable on-chip CAPDAC.
The CAPDAC can be understood as a negative capacitance
connected internally to a CIN pin. The CAPDAC has a 6-bit
resolution and a monotonic transfer function. Figure 24 shows
how to use the CAPDAC to shift the CDC 0 pF to 4 pF input
range to measure capacitance between 10 pF and 14 pF.
INTERFACE
C
0pF TO 4pF
C
10pF TO 14pF
SERIAL
X
X
EXC
CIN
EXC
CIN
Figure 23. CDC Simplified Block Diagram
Figure 24. Using a CAPDAC
CAPDAC
GENERATOR
MODULATOR
EXCITATION
CAPACITANCE-TO-DIGITAL CONVERTER
OUT1
OUT2
10pF
SDA
SCL
CLOCK
Σ-Δ
PROGRAMMING
INTERFACE
DIGITAL
OUTPUTS
(CDC)
0pF TO 4pF
DIGITAL
FILTER
0x0000 TO 0xFFF0
0x0000 TO 0xFFF0
DATA
DATA
AD7156