SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 40
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 40 of 248
- Download datasheet (2Mb)
Programmer’s Model
2.3.2
2-12
Control Register c1
31
TCM Status Register c0
This is a read-only register that enables operating systems to establish if TCM memories
are present. See also TCM Region Register c9 on page 2-29.
You can access the TCM Status Register by reading CP15 register c0 with the Opcode_2
field set to 2. For example:
The format of the TCM Status Register is shown in Figure 2-4.
Register c1 is the Control Register for the ARM926EJ-S processor. This register
specifies the configuration used to enable and disable the caches and MMU. It is
recommended that you access this register using a read-modify-write sequence.
For both reading and writing, the CRm and Opcode_2 fields Should Be Zero. To read
and write this register, use the instructions:
Function
Isize
Copyright © 2001-2003 ARM Limited. All rights reserved.
SBZ/UNP
Reserved
Size
Assoc
M
Len
Table 2-10 Example Cache Type Register format (continued)
Register bits
[11:10]
[9:6]
[5:3]
[2]
[1:0]
17 16 15
present
DTCM
Figure 2-4 TCM Status Register format
Value
b00
b0101 = 16KB
b010 = 4-way
b0
b10 = 8 words per line (32 bytes)
SBZ/UNP
ARM DDI0198D
1 0
present
ITCM
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