SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 148
SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 148 of 248
- Download datasheet (2Mb)
Bus Interface Unit
6-8
ARM926EJ-S
processor
Multi-layer AHB is described in more detail in the Multi-layer AHB Overview.
Multi-AHB systems
It is possible that the ARM926EJ-S instruction and data AHB interfaces can be
connected to separate AHB systems, although there must be a mechanism to support
data side access to the instruction memory. Each AHB system can be running at
different frequencies. The ARM926EJ-S processor is able to cope with this by
providing two HCLKEN inputs:
•
•
Figure 6-2 on page 6-9 shows an example of a Multi-AHB system.
Copyright © 2001-2003 ARM Limited. All rights reserved.
DHCLKEN is used to specify the rising HCLK edge for the system in which the
data BIU is the master
IHCLKEN is used to specify the rising HCLK edge for the system in which the
instruction BIU is the master.
master
master
master
D-side
I-side
DMA
stage
stage
stage
Input
Input
Input
Decode
Decode
Decode
Figure 6-1 Multi-layer AHB system example
Interconnect
matrix
Mux
Mux
Mux
Mux
ARM DDI0198D
Slave
Slave
Slave
Slave
# 1
# 2
# 3
# 4
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