SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 283
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 283 of 284
- Download datasheet (2Mb)
Depipelined address timings 3-15
E
EmbeddedICE
EmbeddedICE Logic 1-4
Exception
Exception entry/exit summary 2-16
Exception priorities 2-22
Exception vectors 2-21
Exceptions 2-16
External bus arrangement 3-17
External connection of unidirectional
External coprocessors 4-15
ARM DDI 0029G
state 3-31
status register B-50
system sppeed access B-31
system state B-24
systems 5-4
target 5-5
test data registers B-14
timing 7-17
watchpoint registers B-40
watchpoint with another exception
watchpoints B-29
logic 5-13
registers
timing B-54
disabling 5-15
timing 7-15
abort 2-19
entering 2-17
FIQ 2-18
IRQ 2-19
leaving 2-18
SWI 2-21
undefined instruction 2-21
bypass B-14
ID code B-14
instruction B-15
scan path select B-15
programming and reading B-41
B-30
programming B-47
function and mapping B-40
data 2-20
prefetch 2-20
buses 3-19
Copyright © 1994-2001. All rights reserved.
F
FIQ mode 2-7
H
Halfword accesses 3-26, 3-27
I
ID code register B-14
Instruction cycle timings
Instruction pipeline 1-2, 1-3, 1-4
Instruction register B-8
Instruction set
Instruction set formats 1-10
Instruction speed summary 6-29
Instructions
branch 6-4
branch and exchange 6-6
branch with link 6-4
coprocessor absent 6-27
coprocessor data operation 6-20
coprocessor data transfer 6-21
coprocessor register transfer 6-25
data operations 6-7
data swap 6-18
exceptions 6-19
instruction speed summary 6-29
load multiple registers 6-15
load register 6-12
multiply 6-9
multiply accumulate 6-9
store multiple registers 6-17
store register 6-14
SWI 6-19
Thumb branch with link 6-5
undefined instructions 6-27
unexecuted instructions 6-28
ARM 1-5
ARM formats 1-11
summary 1-10
Thumb 1-5, 1-19
Thumb formats 1-20
Thumb summary 1-21
LDC 4-10
STC 4-10
Internal cycles 3-7
Interrupt disable bits 2-14
Interrupt latencies 2-23
IRQ mode 2-7
L
LDC 4-10
Link register 2-8
Little-endian 2-4
M
Memory access 1-3
Memory cycle timing
Memory formats 2-4
Merged I-S cycles 3-8
Mode bits 2-15
Modulating MCLK 3-29
N
Nonsequential cycles 3-5
O
Operating modes 2-7
Operating states 2-3
P
PC register 2-8
Pipeline 1-3, 1-4
Pipelined address timings 3-14
Prefetch Abort B-32
Privileged mode access 3-32
Processor operating states 2-3
maximum 2-23
minimum 2-23
summary 3-10
big-endian 2-4
little-endian 2-4
switching states 2-3
follower 4-5
Index-3
Index
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