SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 151
SAM9260
Manufacturer Part Number
SAM9260
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9260.pdf
(802 pages)
5.SAM9260.pdf
(47 pages)
Specifications of SAM9260
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
210 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9260 PDF datasheet #4
- SAM9260 PDF datasheet #5
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6.6
ARM DDI 0029G
Multiply and multiply accumulate
The multiply instructions use special hardware that implements integer multiplication
with early termination. All cycles except the first are internal
The cycle timings are listed in the following tables:
•
•
•
•
In Table 6-5 to Table 6-8 on page 6-10:
•
multiply instruction cycle operations are listed in Table 6-5
multiply accumulate instruction cycle operations are listed in Table 6-6 on
page 6-9
multiply long instruction cycle operations are listed in Table 6-7 on page 6-10
multiply accumulate long instruction cycle operations are listed in Table 6-8 on
page 6-10.
m is the number of cycles required by the multiplication algorithm. See
Instruction speed summary on page 6-29.
Cycle
1
2
•
m
m+1
Cycle
1
2
•
m
Copyright © 1994-2001. All rights reserved.
Address
pc+2L
pc+3L
pc+3L
pc+3L
pc+3L
pc+3L
Address
pc+8
pc+8
pc+12
pc+12
Table 6-6 Multiply accumulate instruction cycle operations
nRW
0
0
0
0
0
nRW
0
0
0
0
MAS[1:0]
i
i
i
i
i
Table 6-5 Multiply instruction cycle operations
MAS[1:0]
2
2
2
2
Data
(pc+2L)
-
-
-
-
Data
(pc+8)
-
-
-
nMREQ
1
1
1
1
0
nMREQ
1
1
1
1
Instruction Cycle Timings
SEQ
0
0
0
0
1
SEQ
0
0
0
0
nOPC
0
1
1
1
1
nOPC
0
1
1
1
6-9
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