SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 101

• Manufacturer Part Number: SAM9260
• Manufacturer: Atmel Corporation

Specifications of SAM9260

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 210 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

3.8
ARM DDI 0029G
Action of ARM7TDMI core in debug state
When the ARM7TDMI core is in debug state, nMREQ and SEQ are forced to indicate
internal cycles. This allows the rest of the memory system to ignore the processor and
function as normal. Because the rest of the system continues operation, the core ignores
aborts and interrupts while in debug state.
The BIGEND signal must not be changed by the system during debug. If BIGEND
changes, not only is there a synchronization problem but the programmer view of the
processor changes without the knowledge of the debugger. Signal nRESET must also
be held stable during debug. If nRESET is driven LOW then the state of the processor
changes without the knowledge of the debugger.
When instructions are executed in debug state, all bus interface outputs, except
nMREQ and SEQ, change asynchronously to the memory system. For example, every
time a new instruction is scanned into the pipeline, the address bus changes. Although
this is asynchronous it does not affect the system as nMREQ and SEQ are forced to
indicate internal cycles regardless of what the rest of the processor is doing. The
memory controller must be designed to ensure that this asynchronous behavior does not
affect the rest of the system.
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Memory Interface
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