SAM7X256 Atmel Corporation, SAM7X256 Datasheet - Page 231
SAM7X256
Manufacturer Part Number
SAM7X256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7X256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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ARM DDI 0029G
When the BYPASS instruction is loaded into the instruction register, all the scan cells
assume their normal system mode of operation. The BYPASS instruction has no effect
on the system pins:
•
•
•
All unused instruction codes default to the BYPASS instruction.
BYPASS does not enable the processor to exit debug state or synchronize to MCLK for
a system speed access while in debug state. You must use RESTART to achieve this.
In the CAPTURE-DR state, a logic 0 is captured the bypass register.
In the SHIFT-DR state, test data is shifted into the bypass register through TDI
and shifted out through TDO after a delay of one TCK cycle. The first bit to shift
out is a zero.
In the UPDATE-DR state, the bypass register is not affected.
Note
Copyright © 1994-2001. All rights reserved.
Debug in Depth
B-13
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