SAM7SE512 Atmel Corporation, SAM7SE512 Datasheet

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... Erase Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit – Fast Flash Programming Interface for High Volume Production • 32 Kbytes (AT91SAM7SE512/256 Kbytes (AT91SAM7SE32) of Internal High-speed SRAM, Single-cycle Access at Maximum Speed • One External Bus Interface (EBI) – ...

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... Fully Static Operation: – MHz at 1.8V and 85° C Worst Case Conditions – MHz at 1.65V and 85° C Worst Case Conditions • Available in a 128-lead LQFP Green Package 144-ball LFBGA RoHS-compliant Package AT91SAM7SE512/256/32 Summary 2 ® Infrared Modulation/Demodulation 6222ES–ATARM–15-Dec-09 ...

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... Atmel's AT91SAM7SE Series is a member of its Smart ARM Microcontroller family based on the 32-bit ARM7 • AT91SAM7SE512 features a 512 Kbyte high-speed Flash and a 32 Kbyte SRAM. • AT91SAM7SE256 features a 256 Kbyte high-speed Flash and a 32 Kbyte SRAM. • AT91SAM7SE32 features a 32 Kbyte high-speed Flash and an 8 Kbyte SRAM. ...

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... Block Diagram Figure 2-1. IRQ0-IRQ1 PCK0-PCK2 VDDFLASH VDDCORE VDDCORE AT91SAM7SE512/256/32 Summary 4 AT91SAM7SE512/256/32 Block Diagram Signal Description ICE TDI TDO JTAG TMS SCAN TCK JTAGSEL System Controller TST FIQ Memory Controller AIC Embedded Flash Controller PDC DRXD DBGU DTXD Abort PDC Status Memory Protection ...

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... Microcontroller Reset TST Test Mode Select DRXD Debug Receive Data DTXD Debug Transmit Data IRQ0 - IRQ1 External Interrupt Inputs FIQ Fast Interrupt Input 6222ES–ATARM–15-Dec-09 AT91SAM7SE512/256/32 Summary Active Type Level Power Power Power Power Power Power Power Ground Clocks, Oscillators and PLLs ...

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... Timer Counter I/O Line B PWM0 - PWM3 PWM Channels MISO Master In Slave Out MOSI Master Out Slave In SPCK SPI Serial Clock NPCS0 SPI Peripheral Chip Select 0 NPCS1-NPCS3 SPI Peripheral Chip Select AT91SAM7SE512/256/32 Summary 6 Active Type Level PIO I/O I/O I/O USB Device Port Analog Analog USART ...

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... CompactFlash Write Enable CFIOR CompactFlash I/O Read Signal CFIOW CompactFlash I/O Write Signal CFRNW CompactFlash Read Not Write Signal CFCS[1:0] CompactFlash Chip Select Lines 6222ES–ATARM–15-Dec-09 AT91SAM7SE512/256/32 Summary Type Two-Wire Interface I/O I/O Analog-to-Digital Converter Analog Analog Input Analog Fast Flash Programming Interface ...

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... SDWE SDRAM Write Enable RAS - CAS Row and Column Signal NBS[3:0] Byte Mask Signals SDA10 SDRAM Address 10 Line Note: 1. Refer to Section 6. “/O Lines Considerations” on page AT91SAM7SE512/256/32 Summary 8 Active Type Level EBI for NAND Flash Support Output Low Output Low Output ...

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... Package The AT91SAM7SE512/256/32 is available in: • 128-lead LQFP package with a 0.5 mm lead pitch. • 10x 10 x 1.4 mm 144-ball LFBGA package with a 0.8 mm lead pitch 4.1 128-lead LQFP Package Outline Figure 4-1 description is given in the Mechanical Characteristics section of the full datasheet. Figure 4-1. 128-lead LQFP Package Outline (Top View) 6222ES– ...

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... GND 54 23 VDDCORE 55 24 PA8/PGMM0 56 25 PA7/PGMNVALID 57 26 PA6/PGMNOE 58 27 PA5/PGMRDY 59 28 PA4/PGMNCMD 60 29 PA3 61 30 PA2/PGMEN2 62 31 PA1/PGMEN1 63 32 PA0/PGMEN0 64 AT91SAM7SE512/256/32 Summary 10 PB31 65 PB30 66 PB29 67 PB28 68 PB27 69 PB26 70 PB25 71 PB24 72 VDDCORE PB23 73 PB22 74 PB21 75 PB20 76 GND 77 VDDIO 78 JTAGSEL VDDCORE 79 ...

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... LFBGA Package Outline Figure 4-2 description is given in the Mechanical Characteristics section. Figure 4-2. 6222ES–ATARM–15-Dec-09 AT91SAM7SE512/256/32 Summary shows the orientation of the 144-ball LFBGA package and a detailed mechanical 144-ball LFBGA Package Outline (Top View ...

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... LFBGA Pinout Table 4-2. SAM7SE512/256/32 Pinout for 144-ball LFBGA Package Pin Signal Name Pin A1 PB7 D1 A2 PB8 D2 A3 PB9 D3 A4 PB12 D4 A5 PB13 D5 A6 PB16 D6 A7 PB22 D7 A8 PB23 D8 A9 PB25 D9 A10 PB29 D10 A11 PB30 D11 A12 PB31 D12 B1 PB6 ...

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... Power Consumption The AT91SAM7SE512/256/32 has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 20 µA static current. ...

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... For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R. 5.4 Typical Powering Schematics The AT91SAM7SE512/256/32 supports a 3.3V single supply mode. The internal regulator input connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. shows the power schematics to be used for USB bus-powered systems. ...

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... AT91SAM7SE512/256/32 when asserted high. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND. ...

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... The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 300 mA. AT91SAM7SE512/256/32 Summary 16 6222ES–ATARM–15-Dec-09 ...

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... Remaps the SRAM in place of the embedded non-volatile memory – Allows handling of dynamic exception vectors • 16-area Memory Protection Unit (Internal Memory and peripheral protection only) 6222ES–ATARM–15-Dec-09 AT91SAM7SE512/256/32 Summary ® high-performance 32-bit instruction set ® high code density 16-bit instruction set ™ ...

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... Chip Select Lines • Multiple Access Modes supported – Byte Write or Byte Select Lines – Two different Read Protocols for each Memory Bank AT91SAM7SE512/256/32 Summary 18 wait states IDE) are supported but the signals _IOIS16 (I/O and True IDE modes) and -ATA SEL (True IDE mode) are not handled. ® ...

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... Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being – Supports 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte 6222ES–ATARM–15-Dec-09 AT91SAM7SE512/256/32 Summary detected erroneous pages 19 ...

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... One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory • Next Pointer management for reducing interrupt latency requirements • Peripheral DMA Controller (PDC) priority is as follows (from the highest priority to the lowest): AT91SAM7SE512/256/32 Summary 20 Receive DBGU ...

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... Memories • 512 Kbytes of Flash Memory (AT91SAM7SE512) – dual plane – two contiguous banks of 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – Page programming without auto-erase – ...

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... MBytes 1,536 MBytes Undefined (Abort) 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256 MBytes 0xFFFF FFFF AT91SAM7SE512/256/32 Summary 22 Internal Memory Mapping 0x0000 0000 Boot Memory (1) 1 MBytes Flash before Remap SRAM after Remap 0x000F FFFF 0x0010 0000 1 MBytes ...

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... SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. 8.1.1.2 Internal ROM The AT91SAM7SE512/256/32 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000. The ROM contains the FFPI and the SAM-BA boot program. 8.1.1.3 Internal Flash • ...

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... Embedded Flash 8.1.2.1 Flash Overview The Flash of the AT91SAM7SE512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. It reads as 131,072 32-bit words. The Flash of the AT91SAM7SE256 is organized in 1024 pages (single plane) of 256 bytes. It reads as 65,536 32-bit words. The Flash of the AT91SAM7SE32 is organized in 256 pages (single plane) of 128 bytes. It reads as 8192 32-bit words ...

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... The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode. • Two EFCs (EFC0 and EFC1) are embedded in the SAM7SE512 to control each plane of 256 KBytes. Dual plane organization allows concurrent Read and Program. ...

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... The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high and PA2 tied to low. • The Flash of the AT91SAM7SE512 is organized in 2048 pages of 256 bytes (dual plane). It reads as 131,072 32-bit words. ...

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... The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 2 is set to 0. 8.2 External Memories The external memories are accessed through the External Bus Interface. Refer to the memory map in 6222ES–ATARM–15-Dec-09 AT91SAM7SE512/256/32 Summary Figure 8-1 on page 22. 27 ...

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... Figure 9-1 on page 29 Figure 8-1 on page 22 erals. Note that the Memory Controller configuration user interface is also mapped within this address space. AT91SAM7SE512/256/32 Summary 28 shows the System Controller Block Diagram. shows the mapping of the User Interface of the System Controller periph- 6222ES–ATARM–15-Dec-09 ...

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... Figure 9-1. NRST XIN XOUT PLLRC PA0-PA31 PB0-PB31 PC0-PC29 6222ES–ATARM–15-Dec-09 AT91SAM7SE512/256/32 Summary System Controller Block Diagram System Controller irq0-irq1 Advanced fiq Interrupt Controller periph_irq[2..18] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK Debug periph_nreset Unit dbgu_rxd Periodic MCK debug Interval ...

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... Brownout Detector and Power On Reset The AT91SAM7SE512/256/32 embeds one brownout detection circuit and a power-on reset cell. The power-on reset is supplied with and monitors VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power- down sequences or if brownouts occur on the VDDCORE power supply. ...

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... The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating fre- quency of the device. The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing reduced power consumption while waiting for an interrupt. 6222ES–ATARM–15-Dec-09 AT91SAM7SE512/256/32 Summary Clock Generator Block Diagram Clock Generator Embedded Oscillator ...

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... Easy debugging by preventing automatic operations • Fast Forcing – Permits redirecting any interrupt source on the fast interrupt • General Interrupt Mask – Provides processor synchronization on events without triggering an interrupt AT91SAM7SE512/256/32 Summary 32 Power Management Controller Block Diagram Master Clock Controller SLCK ...

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... Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x272A 0A40 (VERSION 0) for AT91SAM7SE512 – Chip ID is 0x272A 0940 (VERSION 0) for AT91SAM7SE256 – Chip ID is 0x2728 0340 (VERSION 0) for AT91SAM7SE32 9 ...

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... Synchronous output, provides Set and Clear of several I/O lines in a single write 9.10 Voltage Regulator Controller The purpose of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set). AT91SAM7SE512/256/32 Summary 34 6222ES–ATARM–15-Dec-09 ...

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... EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in 10.2 Peripheral Identifiers The AT91SAM7SE512/256/32 embeds a wide range of peripherals. Peripheral Identifiers of the AT91SAM7SE512/256/32. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller. Table 10-1. Peripheral ID ...

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... Peripheral Multiplexing on PIO Lines The AT91SAM7SE512/256/32 features three PIO controllers, PIOA, PIOB and PIOC, that multi- plex the I/O lines of the peripheral set. PIO Controller A and B control 32 lines; PIO Controller C controls 24 lines. Each line can be assigned to one of two peripheral functions Some of them can also be multiplexed with the analog inputs of the ADC Controller ...

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... PA22 TXD1 PA23 SCK1 PA24 RTS1 PA25 CTS1 PA26 DCD1 PA27 DTR1 PA28 DSR1 PA29 RI1 PA30 IRQ1 PA31 NPCS1 6222ES–ATARM–15-Dec-09 AT91SAM7SE512/256/32 Summary Peripheral B Comments A0/NBS0 High-Drive A1/NBS2 High-Drive A2 High-Drive A3 High-Drive A10 A11 A12 A13 ...

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... PB21 PCK1 PB22 NPCS3 PB23 PWM0 PB24 PWM1 PB25 PWM2 PB26 TIOA2 PB27 TIOB2 PB28 TCLK1 PB29 TCLK2 PB30 NPCS2 PB31 PCK2 AT91SAM7SE512/256/32 Summary 38 Peripheral B Comments A0/NBS0 A1/NBS2 A10 A11 A12 A13 A14 A15 A16/BA0 A17/BA1 D16 ...

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... Four chip selects with external decoder allow communication with – Serial memories, such as DataFlash – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and – External co-processors • Master or slave serial peripheral bus interface 6222ES–ATARM–15-Dec-09 AT91SAM7SE512/256/32 Summary Peripheral B Comments RTS1 DTR1 PCK0 ...

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... Remote Loopback, Local Loopback, Automatic Echo 10.10 Serial Synchronous Controller • Provides serial synchronous communication links used in audio and telecom applications • Contains an independent receiver and transmitter and a common clock divider AT91SAM7SE512/256/32 Summary 40 between clock and data modulation and demodulation 6222ES–ATARM–15-Dec-09 ...

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... Independent clock selection – Independent period and duty cycle, with double buffering – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform 6222ES–ATARM–15-Dec-09 AT91SAM7SE512/256/32 Summary Table 10-4 Timer Counter Clocks Assignment TC Clock input TIMER_CLOCK1 ...

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... Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all • Each analog input shared with digital signals AT91SAM7SE512/256/32 Summary 42 enabled channels 6222ES–ATARM–15-Dec-09 ...

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... Package Drawings Figure 11-1. 128-lead LQFP Package Drawing 6222ES–ATARM–15-Dec-09 AT91SAM7SE512/256/32 Summary 43 ...

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... Figure 11-2. 144-ball LFBGA Package Drawing All dimensions are in mm AT91SAM7SE512/256/32 Summary 44 6222ES–ATARM–15-Dec-09 ...

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... Ordering Information Table 12-1. Ordering Information Ordering Code AT91SAM7SE512-AU AT91SAM7SE256-AU AT91SAM7SE32-AU AT91SAM7SE512-CU AT91SAM7SE256-CU AT91SAM7SE32-CU 6222ES–ATARM–15-Dec-09 AT91SAM7SE512/256/32 Summary Package Package Type LQFP128 Green LQFP128 Green LQFP128 Green LFBGA144 Green LFBGA144 Green LFBGA144 Green Temperature Operating Range Industrial (-40° 85° C) Industrial (-40° ...

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... Features: “Mode for General Purpose Two-wire UART Serial Communication” added to Signal Description: 6222FS Table 3-1, “Signal Description System Controller: Figure 9-1 ”System Controller Block AT91SAM7SE512/256/32 Summary 46 ordering information code reference changed Section 6.3 ”Reset Pin”, Section 6.5 ”SDCK PDC priority list added Controller”, Multiple device adaptability includes: compliant w/PSRAM in Compact Flash not shown w/EBI Chip Select 5. Compact Flash is “ ...

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