SAM7SE512 Atmel Corporation, SAM7SE512 Datasheet
SAM7SE512
Specifications of SAM7SE512
Related parts for SAM7SE512
SAM7SE512 Summary of contents
Page 1
... Erase Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit – Fast Flash Programming Interface for High Volume Production • 32 Kbytes (SAM7SE512/256 Kbytes (SAM7SE32) of Internal High-speed SRAM, Single-cycle Access at Maximum Speed • One External Bus Interface (EBI) – ...
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... Fully Static Operation: – MHz at 1.8V and 85⋅ C Worst Case Conditions – MHz at 1.65V and 85⋅ C Worst Case Conditions • Available in a 128-lead LQFP Green Package 144-ball LFBGA RoHS-compliant Package SAM7SE512/256/32 2 ® Infrared Modulation/Demodulation 6222F–ATARM–14-Jan-11 ...
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... Atmel's SAM7SE Series is a member of its Smart ARM Microcontroller family based on the 32- bit ARM7 • SAM7SE512 features a 512 Kbyte high-speed Flash and a 32 Kbyte SRAM. • SAM7SE256 features a 256 Kbyte high-speed Flash and a 32 Kbyte SRAM. • SAM7SE32 features a 32 Kbyte high-speed Flash and an 8 Kbyte SRAM. ...
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... Block Diagram Figure 2-1. IRQ0-IRQ1 PCK0-PCK2 VDDFLASH VDDCORE VDDCORE SAM7SE512/256/32 4 SAM7SE512/256/32 Block Diagram Signal Description ICE TDI TDO JTAG TMS SCAN TCK JTAGSEL System Controller TST FIQ Memory Controller AIC Embedded Flash Controller PDC DRXD DBGU DTXD Abort PDC Status Memory Protection ...
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... Input Input Flash Memory Input High Reset/Test I/O Low Input High Debug Unit Input Output AIC Input Input SAM7SE512/256/32 Comments 3V to 3.6V 1.85V 3.6V or 1.65V to 1.95V 1.65V to 1.95V 1.65V to 1.95V No pull-up resistor No pull-up resistor No pull-up resistor. (1) Pull-down resistor (1) Pull-down resistor (1) Open drain with pull-up resistor ...
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... Timer Counter I/O Line B PWM0 - PWM3 PWM Channels MISO Master In Slave Out MOSI Master Out Slave In SPCK SPI Serial Clock NPCS0 SPI Peripheral Chip Select 0 NPCS1-NPCS3 SPI Peripheral Chip Select SAM7SE512/256/32 6 Active Type Level PIO I/O I/O I/O USB Device Port Analog Analog USART ...
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... Low Static Memory Controller Output Low Output Low Output Low Output Low Output Low Output Low EBI for CompactFlash Support Output Low Output Low Output Low Output Low Output Low Output Output Low SAM7SE512/256/32 Comments Digital pulled-up inputs at reset Analog Inputs 7 ...
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... Bank Select SDWE SDRAM Write Enable RAS - CAS Row and Column Signal NBS[3:0] Byte Mask Signals SDA10 SDRAM Address 10 Line Note: 1. Refer to Section 6. ”I/O Lines Considerations” SAM7SE512/256/32 8 Active Type Level EBI for NAND Flash Support Output Low Output Low Output Low ...
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... Package The SAM7SE512/256/32 is available in: • 128-lead LQFP package with a 0.5 mm lead pitch. • 10x 10 x 1.4 mm 144-ball LFBGA package with a 0.8 mm lead pitch 4.1 128-lead LQFP Package Outline Figure 4-1 description is given in the Mechanical Characteristics section of the full datasheet. Figure 4-1. 128-lead LQFP Package Outline (Top View) 6222F– ...
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... GND 54 23 VDDCORE 55 24 PA8/PGMM0 56 25 PA7/PGMNVALID 57 26 PA6/PGMNOE 58 27 PA5/PGMRDY 59 28 PA4/PGMNCMD 60 29 PA3 61 30 PA2/PGMEN2 62 31 PA1/PGMEN1 63 32 PA0/PGMEN0 64 SAM7SE512/256/32 10 PB31 65 PB30 66 PB29 67 PB28 68 PB27 69 PB26 70 PB25 71 PB24 72 VDDCORE PB23 73 PB22 74 PB21 75 PB20 76 GND 77 VDDIO 78 JTAGSEL VDDCORE 79 PB19 ...
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... Mechanical Characteristics section. Figure 4-2. 6222F–ATARM–14-Jan-11 shows the orientation of the 144-ball LFBGA package and a detailed mechanical 144-ball LFBGA Package Outline (Top View Ball A1 SAM7SE512/256/32 11 ...
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... LFBGA Pinout Table 4-2. SAM7SE512/256/32 Pinout for 144-ball LFBGA Package Pin Signal Name Pin A1 PB7 D1 A2 PB8 D2 A3 PB9 D3 A4 PB12 D4 A5 PB13 D5 A6 PB16 D6 A7 PB22 D7 A8 PB23 D8 A9 PB25 D9 A10 PB29 D10 A11 PB30 D11 A12 PB31 D12 B1 PB6 ...
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... Power Consumption The SAM7SE512/256/32 has a static current of less than 60 µA on VDDCORE at 25°C, includ- ing the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 20 µA static current. ...
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... For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R. 5.4 Typical Powering Schematics The SAM7SE512/256/32 supports a 3.3V single supply mode. The internal regulator input con- nected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. the power schematics to be used for USB bus-powered systems. ...
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... SAM7SE512/256/32 when asserted high. The TST pin integrates a permanent pull-down resis- tor of about 15 kΩ ...
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... I/O Lines Current Drawing The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 300 mA. SAM7SE512/256/32 16 6222F–ATARM–14-Jan-11 ...
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... Remaps the SRAM in place of the embedded non-volatile memory – Allows handling of dynamic exception vectors • 16-area Memory Protection Unit (Internal Memory and peripheral protection only) 6222F–ATARM–14-Jan-11 ® high-performance 32-bit instruction set ® high code density 16-bit instruction set ™ (Integrated embedded in-circuit emulator) SAM7SE512/256/32 17 ...
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... Chip Select Lines • Multiple Access Modes supported – Byte Write or Byte Select Lines – Two different Read Protocols for each Memory Bank SAM7SE512/256/32 18 wait states IDE) are supported but the signals _IOIS16 (I/O and True IDE modes) and -ATA SEL (True IDE mode) are not handled. ® ...
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... ECC value available in a register • Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being – Supports 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte 6222F–ATARM–14-Jan-11 detected erroneous pages SAM7SE512/256/32 19 ...
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... One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory • Next Pointer management for reducing interrupt latency requirements • Peripheral DMA Controller (PDC) priority is as follows (from the highest priority to the lowest): SAM7SE512/256/32 20 Receive DBGU ...
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... Memories • 512 Kbytes of Flash Memory (SAM7SE512) – dual plane – two contiguous banks of 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – Page programming without auto-erase – ...
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... FFFF 0x9000 0000 6 x 256 MBytes 1,536 MBytes Undefined (Abort) 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256 MBytes 0xFFFF FFFF SAM7SE512/256/32 22 Internal Memory Mapping 0x0000 0000 Boot Memory (1) 1 MBytes Flash before Remap SRAM after Remap 0x000F FFFF 0x0010 0000 1 MBytes ...
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... SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes avail- able at address 0x0. 8.1.1.2 Internal ROM The SAM7SE512/256/32 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000. The ROM contains the FFPI and the SAM-BA boot program. 8.1.1.3 Internal Flash • ...
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... Embedded Flash 8.1.2.1 Flash Overview The Flash of the SAM7SE512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. It reads as 131,072 32-bit words. The Flash of the SAM7SE256 is organized in 1024 pages (single plane) of 256 bytes. It reads as 65,536 32-bit words. The Flash of the SAM7SE32 is organized in 256 pages (single plane) of 128 bytes. It reads as 8192 32-bit words ...
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... The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode. • Two EFCs (EFC0 and EFC1) are embedded in the SAM7SE512 to control each plane of 256 KBytes. Dual plane organization allows concurrent Read and Program. ...
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... The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high and PA2 tied to low. • The Flash of the SAM7SE512 is organized in 2048 pages of 256 bytes (dual plane). It reads as 131,072 32-bit words. ...
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... The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 2 is set to 0. 8.2 External Memories The external memories are accessed through the External Bus Interface. Refer to the memory map in 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Figure 8-1 on page 22. 27 ...
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... F000 and 0xFFFF FFFF. Figure 9-1 on page 29 Figure 8-1 on page 22 erals. Note that the Memory Controller configuration user interface is also mapped within this address space. SAM7SE512/256/32 28 shows the System Controller Block Diagram. shows the mapping of the User Interface of the System Controller periph- 6222F–ATARM–14-Jan-11 ...
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... Controller proc_nreset flash_poe rstc_irq SLCK SLCK periph_clk[2..18] pck[0-3] Power MAINCK Management PCK Controller UDPCK MCK PLLCK pmc_irq int idle SAM7SE512/256/32 jtag_nreset Boundary Scan TAP Controller nirq nfiq proc_nreset ARM7TDMI PCK debug power_on_reset force_ntrst security_bit flash_poe Embedded Flash flash_wrdis cal gpnvm[0..2] MCK ...
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... Brownout Detector and Power On Reset The SAM7SE512/256/32 embeds one brownout detection circuit and a power-on reset cell. The power-on reset is supplied with and monitors VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power- down sequences or if brownouts occur on the VDDCORE power supply. ...
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... Clock Generator Block Diagram Clock Generator Embedded Oscillator XIN Main Oscillator XOUT PLL and Divider PLLRC Status Power Management Controller SAM7SE512/256/32 Slow Clock RC SLCK Main Clock MAINCK PLL Clock PLLCK Control 31 ...
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... Easy debugging by preventing automatic operations • Fast Forcing – Permits redirecting any interrupt source on the fast interrupt • General Interrupt Mask – Provides processor synchronization on events without triggering an interrupt SAM7SE512/256/32 32 Power Management Controller Block Diagram Master Clock Controller SLCK Prescaler MAINCK /1,/2,/4, ...
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... Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x272A 0A40 (VERSION 0) for SAM7SE512 – Chip ID is 0x272A 0940 (VERSION 0) for SAM7SE256 – Chip ID is 0x2728 0340 (VERSION 0) for SAM7SE32 9 ...
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... Synchronous output, provides Set and Clear of several I/O lines in a single write 9.10 Voltage Regulator Controller The purpose of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set). SAM7SE512/256/32 34 6222F–ATARM–14-Jan-11 ...
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... EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in 10.2 Peripheral Identifiers The SAM7SE512/256/32 embeds a wide range of peripherals. Identifiers of the SAM7SE512/256/32. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller. Table 10-1. Peripheral ID ...
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... Peripheral Multiplexing on PIO Lines The SAM7SE512/256/32 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. PIO Controller A and B control 32 lines; PIO Controller C controls 24 lines. Each line can be assigned to one of two peripheral functions Some of them can also be multiplexed with the analog inputs of the ADC Controller ...
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... Comments A0/NBS0 High-Drive A1/NBS2 High-Drive A2 High-Drive A3 High-Drive A10 A11 A12 A13 A14 A15 A16/BA0 A17/BA1 AD0 NBS3/CFIOW AD1 NCS4/CFCS0 AD2 NCS2/CFCS1 AD3 NCS6/CFCE2 NCS5/CFCE1 NWR1/NBS1/CFIOR SDA10 SDCKE NCS1/SDCS SDWE CAS RAS D30 D31 SAM7SE512/256/32 Application Usage Function Comments 37 ...
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... IRQ0 PB21 PCK1 PB22 NPCS3 PB23 PWM0 PB24 PWM1 PB25 PWM2 PB26 TIOA2 PB27 TIOB2 PB28 TCLK1 PB29 TCLK2 PB30 NPCS2 PB31 PCK2 SAM7SE512/256/32 38 Peripheral B Comments A0/NBS0 A1/NBS2 A10 A11 A12 A13 A14 A15 A16/BA0 A17/BA1 D16 ...
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... External co-processors • Master or slave serial peripheral bus interface 6222F–ATARM–14-Jan-11 Peripheral B Comments RTS1 DTR1 PCK0 PCK1 PCK2 NPCS1 NCS3/NANDCS NWAIT NANDOE NANDWE NCS7 NWR0/NWE/CFWE NRD/CFOE NCS0 peripherals Sensors SAM7SE512/256/32 Application Usage Function Comments ® and 3-wire EEPROMs 39 ...
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... Remote Loopback, Local Loopback, Automatic Echo 10.10 Serial Synchronous Controller • Provides serial synchronous communication links used in audio and telecom applications • Contains an independent receiver and transmitter and a common clock divider SAM7SE512/256/32 40 between clock and data modulation and demodulation 6222F–ATARM–14-Jan-11 ...
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... Independent period and duty cycle, with double buffering – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform 6222F–ATARM–14-Jan-11 Table 10-4 Timer Counter Clocks Assignment TC Clock input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 SAM7SE512/256/32 Clock MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024 41 ...
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... External trigger pin – Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all • Each analog input shared with digital signals SAM7SE512/256/32 42 enabled channels 6222F–ATARM–14-Jan-11 ...
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... The main features of the ARM7tDMI processor are: • ARM7TDMI Based on ARMv4T Architecture • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • Three-Stage Pipeline Architecture – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 43 ...
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... At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing. Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention stack pointer. SAM7SE512/256/32 44 6222F–ATARM–14-Jan-11 ...
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... R10 R10 R11 R11 R12 R12 R13_SVC R13_ABORT R14_SVC R14_ABORT PC PC CPSR CPSR SPSR_SVC SPSR_ABORT SAM7SE512/256/32 Undefined Interrupt Fast Interrupt Mode Mode Mode ...
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... Status register transfer instructions • Load and Store instructions • Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]). SAM7SE512/256/32 46 supports five types of exception and a privileged processing mode for each type. 6222F–ATARM–14-Jan-11 ...
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... Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move To Coprocessor Load To Coprocessor SAM7SE512/256/32 Mnemonic Operation CDP Coprocessor Data Processing MVN Move Not ADC Add with Carry SBC ...
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... TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH SAM7SE512/256/32 48 gives the Thumb instruction mnemonic list. Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply ...
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... A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 12.2 Block Diagram Figure 12-1. Debug and Test Block Diagram PDC 6222F–ATARM–14-Jan-11 ICE/JTAG Boundary TAP TAP ICE ARM7TDMI DBGU SAM7SE512/256/32 TMS TCK TDI JTAGSEL TDO POR Reset and Test TST DTXD DRXD 49 ...
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... Application Examples 12.3.1 Debug Environment Figure 12-2 standard debugging functions, such as downloading code and single-stepping through the program. Figure 12-2. Application Debug Environment Example SAM7SE512/256/32 50 shows a complete debug environment example. The ICE/JTAG interface is used for ICE/JTAG Interface ICE/JTAG Connector RS232 AT91SAMSExx Connector AT91SAM7Sxx-based Application Board ...
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... Microcontroller Reset Test Mode Select ICE and JTAG Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Debug Unit Debug Receive Data Debug Transmit Data SAM7SE512/256/32 Tester Chip 2 Chip 1 Type Active Level Input/Output Input Input Input Output Input ...
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... AT91SAM7SE256 AT91SAM7SE512 For further details on the Debug Unit, see the Debug Unit section. 12.5.4 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. SAM7SE512/256/32 52 AT91SAM7SExx Chip IDs Chip ID 0x27280340 0x272A0940 0x272A0A40 6222F–ATARM–14-Jan-11 ...
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... The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. For more information, please refer to BDSL files which are available for the SAM7SE Series. 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 53 ...
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... VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Chip Name AT91SAM7SE32 AT91SAM7SE256 AT91SAM7SE512 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. • Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. Chip Name AT91SAM7SE32 AT91SAM7SE256 AT91SAM7SE512 SAM7SE512/256/ PART NUMBER ...
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... A brownout detection is also available to prevent the processor from falling into an unpredictable state. 13.1 Block Diagram Figure 13-1. Reset Controller Block Diagram Main Supply 6222F–ATARM–14-Jan-11 Reset Controller bod_rst_en Brownout Manager brown_out Startup POR Counter NRST NRST Manager nrst_out WDRPROC wd_fault SAM7SE512/256/32 bod_reset Reset State rstc_irq Manager proc_nreset user_reset periph_nreset exter_nreset SLCK 55 ...
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... The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. SAM7SE512/256/32 56 Figure 13-2 shows the block diagram of the NRST Manager. ...
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... It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 6222F–ATARM–14-Jan-11 Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs bod_rst_en RSTC_SR brown_out BODSTS SAM7SE512/256/32 bod_reset RSTC_MR BODIEN rstc_irq Other interrupt sources ...
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... EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How- ever, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. SAM7SE512/256/32 58 Figure 13-4, is hardcoded to comply with the Slow Clock Oscillator ...
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... An external reset is also triggered. When the processor reset is released, the field RSTTYP in RSTC_SR is loaded with the value 0x5, thus indicating that the last reset is a Brownout Reset. 6222F–ATARM–14-Jan-11 Resynch. 2 cycles XXX >= EXTERNAL RESET LENGTH SAM7SE512/256/32 Processor Startup = 3 cycles 0x4 = User Reset 59 ...
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... ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. SAM7SE512/256/32 60 Resynch. Processor Startup ...
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... When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. 6222F–ATARM–14-Jan-11 SLCK Any MCK Freq. Write RSTC_CR Resynch. 1 cycle proc_nreset if PROCRST=1 RSTTYP Any periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 SRCMP in RSTC_SR SAM7SE512/256/32 Processor Startup = 3 cycles XXX 0x3 = Software Reset EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 61 ...
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... The NRST has no effect. • When in Watchdog Reset: – The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered. 13.2.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: SAM7SE512/256/32 62 SLCK Any MCK Freq. wd_fault ...
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... Reset Controller (RSTC) User Interface Table 13-1. Reset Controller (RSTC) Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 read RSTC_SR 2 cycle resynchronization Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read/Write Figure ...
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... No effect KEY is correct, resets the peripherals. • EXTRST: External Reset effect KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM7SE512/256/ KEY 21 ...
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... Comments VDDCORE rising Watchdog fault occurred Processor reset required by the software NRST pin detected low Brownout reset occurred SAM7SE512/256/ – – – – SRCMP NRSTL RSTTYP – ...
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... This field defines the external reset length. The external reset is asserted during a time of 2 allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM7SE512/256/ ...
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... RTT_SR RTTINC reset 1 0 32-bit Counter read RTT_SR reset CRTV RTT_SR ALMS set = ALMV SAM7SE512/256/32 RTT_MR RTTINCIEN rtt_int RTT_MR ALMIEN rtt_alarm 32 seconds, corre- 67 ...
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... RTPRES - 1 RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface SAM7SE512/256/32 68 Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. ...
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... Real-time Timer (RTT) User Interface Table 14-1. Real-time Timer (RTT) Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Name Access RTT_MR Read/Write RTT_AR Read/Write RTT_VR Read-only RTT_SR Read-only Reset Value 0x0000_8000 0xFFFF_FFFF ...
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... RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. SAM7SE512/256/ – ...
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... CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 6222F–ATARM–14-Jan- ALMV ALMV ALMV ALMV CRTV CRTV CRTV CRTV SAM7SE512/256/ ...
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... The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR The Real-time Timer has been incremented since the last read of the RTT_SR. SAM7SE512/256/ – ...
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... WDT_MR WDT_CR WDRSTT WDT_MR read WDT_SR or reset 6222F–ATARM–14-Jan-11 WDT_MR WDV reload 1 0 12-bit Down Counter WDD Current Value <= WDD = 0 set WDUNF reset set WDERR reset SAM7SE512/256/32 reload SLCK 1/128 WDT_MR WDRSTEN wdt_fault (to Reset Controller) wdt_int WDFIEN WDT_MR 73 ...
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... Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. SAM7SE512/256/32 74 6222F–ATARM–14-Jan-11 ...
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... Figure 15-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault 6222F–ATARM–14-Jan-11 Watchdog Error WDT_CR = WDRSTT SAM7SE512/256/32 Watchdog Underflow if WDRSTEN WDRSTEN ...
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... WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM7SE512/256/32 76 Name WDT_CR WDT_MR WDT_SR KEY – ...
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... WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. 6222F–ATARM–14-Jan- WDDBGHLT WDD WDFIEN WDV SAM7SE512/256/ WDD WDV ...
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... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. SAM7SE512/256/ – ...
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... Block Diagram Figure 16-1. Periodic Interval Timer 0 MCK 20-bit Counter MCK/16 CPIV Prescaler CPIV 6222F–ATARM–14-Jan-11 PIT_MR PIV = ? 0 1 PIT_PIVR PIT_PIIR SAM7SE512/256/32 set 0 PIT_SR PITS reset 0 1 12-bit Adder read PIT_PIVR PICNT PICNT PIT_MR PITIEN pit_irq 79 ...
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... PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. SAM7SE512/256/32 80 Figure 16-2 illustrates 6222F– ...
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... Figure 16-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6222F–ATARM–14-Jan-11 MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR SAM7SE512/256/32 APB cycle APB cycle restarts MCK Prescaler ...
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... Periodic Interval Timer (PIT) User Interface Table 16-1. Periodic Interval Timer (PIT) Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register SAM7SE512/256/32 82 Name Access PIT_MR Read/Write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR Read-only Reset Value ...
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... PIV PIV – – – – – – – – – – – – SAM7SE512/256/ – PITIEN PITEN PIV – – – – – – – ...
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... PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. SAM7SE512/256/ PICNT ...
Page 85
... Mode Register. Its offset is 0x60 with respect to the System Controller offset. This register controls the Voltage Regulator Mode. Setting PSTDBY (bit 0) puts the Voltage Regulator in Standby Mode or Low-power Mode. On reset, the PSTDBY is reset wake up the Voltage Regulator in Normal Mode. 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 85 ...
Page 86
... Read/Write 31 30 – – – – – – – – • PSTDBY: Periodic Interval Value 0 = Voltage regulator in normal mode Voltage regulator in standby mode (low-power mode). SAM7SE512/256/32 86 Name VREG_MR – – – – – – – ...
Page 87
... Controller 6222F–ATARM–14-Jan-11 Memory Controller ASB Abort Status Address Misalignment Decoder Detector Bus Arbiter Memory Protection Unit User Interface APB Bridge Peripheral 0 APB Peripheral 1 Peripheral N SAM7SE512/256/32 Embedded Internal Flash Flash Controller Internal RAM External Bus Interface From Master to Slave 87 ...
Page 88
... Eight 256-Mbyte address spaces, each assigned to one of the eight chip select lines of the External Bus Interface • One 256-Mbyte address space reserved for the embedded peripherals • An undefined address space of 1536M bytes that returns an Abort if accessed SAM7SE512/256/32 88 6222F–ATARM–14-Jan-11 ...
Page 89
... FFFF 0x8000 0000 256M Bytes 0x8FFF FFFF 0x9000 0000 6 x 256M Bytes 1,536 bytes 0xEFFF FFFF 0xF000 0000 256M Bytes 0xFFFF FFFF SAM7SE512/256/32 Internal Memories Chip Select 0 Chip Select 1 Chip Select 2 EBI Chip Select 3 External Bus Interface Chip Select 4 Chip Select 5 ...
Page 90
... The Remap Command can be cancelled by writing the MC_RCR RCB field to one, which acts as a toggling command. This allows easy debug of the user-defined boot sequence by offering a simple way to put the chip in the same configuration as after a reset. SAM7SE512/256/32 90 0x0000 0000 Internal Memory Area 0 ...
Page 91
... The peripheral address space and each internal memory area can be protected against write and non-privileged access of one of the masters. When one of the masters performs a forbidden access, an Abort is generated and the Abort Status traces what has happened. 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Figure 18-1. 91 ...
Page 92
... As the requested address is saved in the Abort Status Register and the address of the instruc- tion generating the misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bugs is simplified. SAM7SE512/256/32 92 6222F–ATARM–14-Jan-11 ...
Page 93
... EFC0 Configuration Registers 0x70 EFC1 Configuration Registers 0x80 External bus Interface Registers 0x90 SMC Configuration Registers 0xB0 SDRAMC Configuration Registers 0xDC ECC Configuration Registers 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Name Access MC_RCR Write-only MC_ASR Read-only MC_AASR Read-only MC_PUIA0 Read/Write MC_PUIA1 Read/Write ...
Page 94
... RCB: Remap Command Bit 0: No effect. 1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices. SAM7SE512/256/ – – – – ...
Page 95
... Abort Size Byte Half-word Word Reserved Abort Type Data Read Data Write Code Fetch Reserved SAM7SE512/256/ – SVMST1 18 17 – MST1 10 9 ABTTYP ABTSZ 2 1 MPU MISADD 24 SVMST0 16 MST0 8 0 UNDADD ...
Page 96
... SVMST0: Saved PDC Abort Source 0: No abort due to the PDC occurred least one abort due to the PDC occurred. • SVMST1: Saved ARM7TDMI Abort Source 0: No abort due to the ARM7TDMI occurred least one abort due to the ARM7TDMI occurred. SAM7SE512/256/32 96 6222F–ATARM–14-Jan-11 ...
Page 97
... Absolute Address: 0xFFFF FF08 • ABTADD: Abort Address This field contains the address of the last aborted access. 6222F–ATARM–14-Jan- ABTADD ABTADD ABTADD ABTADD SAM7SE512/256/ ...
Page 98
... BA: Internal Area Base Address These bits define the Base Address of the area. Note that only the most significant bits of BA are significant. The number of significant bits are in respect with the size of the area. SAM7SE512/256/ – – ...
Page 99
... Read/Write 6222F–ATARM–14-Jan- – – – – – – – – Processor Mode Privilege User No access No access Read-only Read/Write SAM7SE512/256/ – – – – – – – – – – – 24 – ...
Page 100
... PUEB: Protection Unit Enable Bit 0: The Memory Controller Protection Unit is disabled. 1: The Memory Controller Protection Unit is enabled. SAM7SE512/256/32 100 – – – – – – – ...
Page 101
... Code Fetch with its system of 32-bit buffers. It also manages the programming, erasing, locking and unlocking sequences using a full set of commands. The SAM7SE512 is equipped with two EFCs, EFC0 and EFC1. EFC1 does not feature the Security bit and GPNVM bits. The Security bit and GPNVM bits embedded only on EFC0 apply to the two blocks in the SAM7SE512 ...
Page 102
... The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it. SAM7SE512/256/32 102 Flash Memory ...
Page 103
... Bytes 4-7 Bytes 8-11 Bytes 4-7 Bytes 0-3 Bytes 2-3 Bytes 4-5 Bytes 6-7 1 Wait State Cycle @Byte 2 @Byte 4 @Byte 6 Bytes 0-3 Bytes 4-7 Bytes 0-3 Bytes 0-1 Bytes 2-3 Bytes 4-5 SAM7SE512/256/32 @Byte 14 @Byte 10 @Byte 12 Bytes 12-15 Bytes 8-11 Bytes 12-15 Bytes 8-9 Bytes 10-11 Bytes 12-13 1 Wait State Cycle 1 Wait State Cycle @Byte 12 @Byte 8 @Byte 10 Bytes 12-15 Bytes 8-11 Bytes 4-7 ...
Page 104
... Flash erasing. Table 19-1. Command Write page Set Lock Bit Write Page and Lock Clear Lock Bit Erase all Set General-purpose NVM Bit Clear General-purpose NVM Bit Set Security Bit SAM7SE512/256/32 104 3 Wait State Cycles 3 Wait State Cycles @ Bytes 4-7 Bytes 0-3 0-1 ...
Page 105
... When the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane; however, the LOCKE flag is set in the MC_FSR register. This flag is automatically cleared by a read access to the MC_FSR register. 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 105 ...
Page 106
... NEBP bit in the MC_FMR register before writing the command in the MC_FCR register. By setting the NEBP bit in the MC_FMR register, a page can be programmed in several steps if it has been erased before (see SAM7SE512/256/32 106 Read Status: MC_FSR No ...
Page 107
... ... Step 2. Programming of the second part of Page 7 (NEBP = 1) Writing of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption. SAM7SE512/256/32 32 bits wide ... ... ...
Page 108
... The Unlock command programs the lock bit to 1; the corresponding bit LOCKSx in MC_FSR reads 0. The Lock command programs the lock bit to 0; the corresponding bit LOCKSx in MC_FSR reads 1. Note: SAM7SE512/256/32 108 Access to the Flash in Read Mode is permitted when a Lock or Unlock command is performed. 6222F–ATARM–14-Jan-11 ...
Page 109
... The goal of the security bit is to prevent external access to the internal bus system. (Does not apply to EFC1 on the SAM7SE512.) JTAG, Fast Flash Programming and Flash Serial Test Inter- face features are disabled. Once set, this bit can be reset only by an external hardware ERASE request to the chip ...
Page 110
... The User Interface of the EFC is integrated within the Memory Controller with Base Address: 0xFFFF FF00. The SAM7SE512 is equipped with two EFCs, EFC0 and EFC1, as described in the Register Mapping tables and Register descriptions that follow. The SAM7SE256/32 is equipped with one EFC (EFC0). ...
Page 111
... FMCN – – – – – PROGE Read Operations 1 cycle 2 cycles 3 cycles 4 cycles SAM7SE512/256/ – – – – FWS LOCKE – FRDY Write Operations 2 cycles 3 cycles 4 cycles 4 cycles 111 ...
Page 112
... When writing the rest of the Flash, this field defines the number of Master Clock cycles in 1.5 microseconds. This number must be rounded up. Warning: The value 0 is only allowed for a master clock period superior to 30 microseconds. Warning: In order to guarantee valid operations on the flash memory, the field Flash Microsecond Cycle Number (FMCN) must be correctly programmed. SAM7SE512/256/32 112 6222F–ATARM–14-Jan-11 ...
Page 113
... Clear General Purpose NVM Bit (CGPB): Deactivates the general-purpose NVM bit corresponding to the number specified in the PAGEN field. Set Security Bit Command (SSB): Sets security bit. Reserved. Raises the Programming Error Status flag in the Flash Status Register MC_FSR. SAM7SE512/256/ – ...
Page 114
... KEY: Write Protection Key This field should be written with the value 0x5A to enable the command defined by the bits of the register. If the field is writ- ten with a different value, the write is not performed and no action is started. SAM7SE512/256/32 114 PAGEN Description PAGEN defines the page number to be written. ...
Page 115
... SECURITY: Security Bit Status (Does not apply to EFC1 on the SAM7SE512.) 0: The security bit is inactive. 1: The security bit is active. • GPNVMx: General-purpose NVM Bit Status (Does not apply to EFC1 on the SAM7SE512.) 0: The corresponding general-purpose NVM bit is inactive. 1: The corresponding general-purpose NVM bit is active. ...
Page 116
... SAM7SE512/256/32 116 6222F–ATARM–14-Jan-11 ...
Page 117
... IEEE 1149.1 JTAG protocol. It offers an optimized access to all the embedded Flash functionalities. Although the Fast Flash Programming Mode is a dedicated mode for high volume programming, this mode not designed for in-situ programming. 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 117 ...
Page 118
... Main Clock Input. This input can be tied to GND. In this XIN case, the device is clocked by the internal RC oscillator. TST Test Mode Select PGMEN0 Test Mode Select PGMEN1 Test Mode Select SAM7SE512/256/32 118 TST VDDIO PGMEN0 VDDIO VDDIO PGMEN1 NCMD PGMNCMD RDY PGMRDY ...
Page 119
... Input/Output Mode Coding Symbol Data CMDE Command Register ADDR0 Address Register LSBs ADDR1 DATA Data Register IDLE No register SAM7SE512/256/32 Active Level Comments Low Pulled-up input at reset High Pulled-up input at reset Low Pulled-up input at reset Low Pulled-up input at reset Pulled-up input at reset ...
Page 120
... GFB SSE GSE WRAM SEFC GVE 1. Applies to SAM7SE512 external clock is available. POR_RESET POR_RESET After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal external clock (> 32 kHz) is connected to XIN, then the device switches on the external clock. Else, XIN input is not considered. A higher frequency on XIN speeds up the programmer handshake ...
Page 121
... NOE NVALID DATA[15:0] 1 MODE[3:0] Device Action Waits for NCMD low Latches MODE and DATA Clears RDY signal Executes command and polls NCMD high Executes command and polls NCMD high Sets RDY SAM7SE512/256/32 Figure 20-2and Table 20- Data I/O Input Input Input Input ...
Page 122
... Waits for NVALID low 7 8 Reads value on DATA Bus 9 Sets NOE signal 10 Waits for NVALID high 11 Sets DATA in output mode 12 Sets NCMD signal 13 Waits for RDY high SAM7SE512/256/32 122 Parallel Programming Timing, Read Sequence NCMD 2 3 RDY NOE NVALID 4 DATA[15:0] Adress IN 1 ADDR ...
Page 123
... ADDR1 Write handshaking ADDR2 Write handshaking ADDR3 Read handshaking DATA Read handshaking DATA ... ... SAM7SE512/256/32 DATA[15:0] READ 32-bit Memory Address First byte 32-bit Flash Address *Memory Address++ *Memory Address++ ... 32-bit Memory Address First byte 32-bit Flash Address 32-bit Flash Address 32-bit Flash Address Last Byte ...
Page 124
... This command is used to erase the Flash memory planes. All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the erase command is aborted and no page is erased. Table 20-8. Step 1 2 SAM7SE512/256/32 124 Write Command Handshake Sequence MODE[3:0] Write handshaking CMDE ...
Page 125
... Handshake Sequence Write handshaking Write handshaking Handshake Sequence Write handshaking Read handshaking Handshake Sequence Write handshaking Write handshaking Handshake Sequence Write handshaking Read handshaking SAM7SE512/256/32 MODE[3:0] DATA[15:0] CMDE SLB or CLB DATA Bit Mask th lock bit is active when the bit MODE[3:0] DATA[15:0] CMDE ...
Page 126
... Fast Flash programming is disabled. No other command can be run. An event on the Erase pin can erase the security bit once the contents of the Flash have been erased. The SAM7SE512 security bit is controlled by the EFC0. To use the Set Security Bit command, the EFC0 must be selected using the Select EFC command. ...
Page 127
... The Get Version (GVE) command retrieves the version of the FFPI interface. Table 20-16. Get Version Command Step 1 2 6222F–ATARM–14-Jan-11 Handshake Sequence MODE[3:0] Write handshaking DATA Write handshaking DATA ... ... Handshake Sequence Write handshaking Write handshaking SAM7SE512/256/32 DATA[15:0] *Memory Address++ *Memory Address++ ... MODE[3:0] DATA[15:0] CMDE GVE DATA Version 127 ...
Page 128
... I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL Power Supply GND Ground Main Clock Input. This input can be tied to GND. In this XIN case, the device is clocked by the internal RC oscillator. SAM7SE512/256/32 128 TST VDDIO VDDIO PGMEN0 VDDIO PGMEN1 TDI TDO TMS TCK ...
Page 129
... Else, XIN input is not considered. An higher frequency on XIN speeds up the programmer handshake. TDI TMS SAM7SE512/256/32 Active Level Comments High Must be connected to VDDIO. High Must be connected to VDDIO High Must be connected to VDDIO - Pulled-up input at reset - Pulled-up input at reset - - Pulled-up input at reset ) if an external clock is available. ...
Page 130
... The read handshake is done by polling the Debug Comms Control Register until the W bit is set. Once set, data can be read in the Debug Comms Data Register. 20.3.4 Device Operations Several commands on the Flash memory are available. These commands are summarized in Table 20-3 on page is reading and writing the Debug Comms Registers. SAM7SE512/256/32 130 r/w Address ...
Page 131
... DR Data (Number of Words to Read) << READ Address Memory [address] Memory [address+4] ... Memory [address+(Number of Words to Read - 1 Data (Number of Words to Write) << (WP or WPL or EWP or EWPL) Address Memory [address] Memory [address+4] Memory [address+8] Memory [address+(Number of Words to Write - 1)* 4] SAM7SE512/256/32 131 ...
Page 132
... In the same way, the Clear Fuse command (CFB) is used to clear GP NVM bits. All the general- purpose NVM bits are also cleared by the EA command. Table 20-24. Set and Clear General-purpose NVM Bit Command Read/Write Write Write SAM7SE512/256/32 132 DR Data EA DR Data SLB or CLB ...
Page 133
... Fast Flash programming is disabled. No other command can be run. Only an event on the Erase pin can erase the security bit once the contents of the Flash have been erased. The SAM7SE512 security bit is controlled by the EFC0. To use the Set Security Bit command, the EFC0 must be selected using the Select EFC command. ...
Page 134
... Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 20-29. Get Version Command Read/Write Write Read SAM7SE512/256/32 134 DR Data GVE Version 6222F–ATARM–14-Jan-11 ...
Page 135
... Memory Controllers. 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 ® and the NAND Flash protocols via integrated circuitry ...
Page 136
... Block Diagram Figure 21-1. Organization of the External Bus Interface Memory Controller ASB Address Decoder SAM7SE512/256/32 136 External Bus Interface SDRAM Controller MUX Logic Static Memory Controller CompactFlash Logic NAND Flash Logic ECC Controller Chip Select Assignor User Interface APB SDCK D[31:0] A0/NBS0 A1/NBS2 ...
Page 137
... Row and Column Signal NBS[3:0] Byte Mask Signals SDA10 SDRAM Address 10 Line 6222F–ATARM–14-Jan-11 EBI SMC EBI for CompactFlash Support EBI for NAND Flash Support SDRAM Controller SAM7SE512/256/32 Type Active Level I/O Output Input Low Output Low Output Low Output ...
Page 138
... A12 A12 A13 - A14 A13 - A14 A15 A15 A16/BA0 A16 A17/BA1 A17 SAM7SE512/256/32 138 details the connections between the two Memory Controllers and the EBI pins. EBI Pins and Memory Controllers I/O Lines Connections SDRAMC I/O Lines NBS1 Not Supported Not Supported A[9:0] A10 ...
Page 139
... CAS – – WE – – – – – – – – – – – – “Using SDRAM on AT91SAM7SE Microcontrollers”, SAM7SE512/256/32 CompactFlash CompactFlash True IDE Mode SMC – – – – REG – (4) (4) CFRNW CFRNW – – (4) (4) ...
Page 140
... When the NAND Flash Logic is used, NWR0/NWE/CFWE must be kept as PIO Input Mode with Pull-up enabled (default state after reset PIO Output set at logic level 1. The PIO cannot be used in PIO Mode. 21.4.2 Connection Examples Figure 21-2 Figure 21-2. EBI Connections to Memory Devices SAM7SE512/256/32 140 shows an example of connections between the EBI and external devices. EBI D0-D31 RAS ...
Page 141
... NCS2 address space. Programming the CS4A and/or CS2A bit of the Chip Select Assignment Register enables this logic. Access to an external CompactFlash device is then made by accessing the 6222F–ATARM–14-Jan-11 (See “EBI Chip Select Assignment Register” on page SAM7SE512/256/32 158.) to the appropriate value 141 ...
Page 142
... NUB and NLB are the byte selection signals from SMC and are available when the SMC is set in Byte Select mode on the corresponding Chip Select. The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For details on these waveforms and timings, refer to the Static Memory Controller Section. SAM7SE512/256/32 142 Offset 0x00E0 0000 Offset 0x00C0 0000 ...
Page 143
... Care 1 8 bits Access to Odd Byte on D[7:0] Don’t 1 Don’t Care Care shows a schematic representation of this logic and SAM7SE512/256/32 SMC Access Mode Byte Select Byte Select Don’t Care Byte Select Don’t Care Don’t Care Byte Select Don’t Care Don’ ...
Page 144
... Register is set must not be used to drive any other memory devices. The EBI pins in CompactFlash interface is enabled (CS4A = 1 and/or CS2A = 1). Table 21-6. Dedicated CompactFlash Interface Multiplexing Pins CS4A = 1 NCS4/CFCS0 CFCS0 NCS2/CFCS1 SAM7SE512/256/32 144 External Bus Interface SMC A22 A21 NRD NWR0_NWE CFWE NRD NWR0_NWE ...
Page 145
... CFWE CFIOR CFIOW CFRNW illustrates an example of a CompactFlash application. CFCS0 and D[15:0] NCS0/CFRNW NCS4/CFCS0 CD (PIO) A[10:0] A22/REG NRD/CFOE NWE/CFWE NWR1/CFIOR CFIOW NCS5/CFCE1 NCS6/CFCE2 NWAIT SAM7SE512/256/32 Access to Other EBI Devices EBI Signals NRD NWR0/NWE NWR1/NBS1 NBS3 NCS0 D[15:0] DIR /OE _CD1 _CD2 /OE A[10:0] _REG _OE _WE _IORD ...
Page 146
... NCS3 address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NCS3 is not selected, preventing the device from returning to standby mode. SAM7SE512/256/32 146 (See “EBI Chip Select Assignment Register” on page ...
Page 147
... Figure 21-7. NAND Flash Application Example Note: 6222F–ATARM–14-Jan-11 D[7:0] A22/REG/NANDCLE A21/NANDALE NCS3/NANDCS EBI NANDOE NANDWE PIO PIO The External Bus Interface is also able to support 16-bit devices. SAM7SE512/256/32 AD[7:0] CLE ALE Not Connected NAND Flash NOE NWE CE R/B 147 ...
Page 148
... Select Assignment Register. • Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The data bus width programmed to 16 bits. The SDRAM initialization sequence is described in the “SDRAM Device Initialization” section of the SDRAM Controller. SAM7SE512/256/32 148 ...
Page 149
... C7 100NF C7 100NF DQML VDDQ 39 DQMH 28 VSS 17 41 CAS VSS 18 54 RAS VSS 6 VSSQ 12 VSSQ VSSQ VSSQ 256 Mbits TSOP54 PACKAGE SAM7SE512/256/ DQ0 MT48LC16M16A2 MT48LC16M16A2 DQ1 DQ2 DQ3 DQ4 ...
Page 150
... A21 and A22 during accesses. • Configure a PIO line as an input to manage the Ready/Busy signal. • Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode according to NAND Flash timings, the data bus width and the system bus frequency. SAM7SE512/256/32 150 U1 U1 ...
Page 151
... R/B 10K 10K 3V3 10K 10K 1 N.C 2 N.C 3 N.C 4 N.C 5 N.C 6 N.C 10 N.C 11 N.C 14 N.C 15 N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 N.C 34 N.C 35 N.C SAM7SE512/256/32 MT29F2G16AABWP-ET MT29F2G16AABWP I/O9 D10 31 I/O10 D11 33 I/O11 D12 41 I/O12 D13 43 I/O13 D14 45 I/O14 D15 47 ...
Page 152
... The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows access on 16-bit non-volatile memory at slow clock. For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency. SAM7SE512/256/32 152 ...
Page 153
... SN74ALVC125 10K 10K RDY/BSY 11 12 MN4 MN4 5 1 3V3 VCC VCC R4 R4 10K 10K WAIT GND GND SN74LVC1G125-Q1 SN74LVC1G125-Q1 SAM7SE512/256/32 MEMORY & I/O MODE J1 J1 CF_D15 31 38 D15 VCC CF_D14 30 D14 CF_D13 29 13 D13 VCC CF_D12 28 D12 CF_D11 27 D11 CF_D10 49 50 ...
Page 154
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode accordingly to CompactFlash timings and system bus frequency. SAM7SE512/256/32 154 6222F–ATARM–14-Jan-11 ...
Page 155
... INTRQ 11 12 3V3 MN4 MN4 5 1 3V3 VCC VCC R4 R4 10K 10K IORDY GND GND SN74LVC1G125-Q1 SN74LVC1G125-Q1 SAM7SE512/256/32 TRUE IDE MODE J1 J1 CF_D15 31 38 D15 VCC CF_D14 30 D14 CF_D13 29 13 D13 VCC CF_D12 28 D12 CF_D11 27 D11 CF_D10 49 50 ...
Page 156
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode according to CompactFlash timings and system bus frequency. SAM7SE512/256/32 156 Figure 21-3). ...
Page 157
... SMC User Interface 0x30 - 0x58 SDRAMC User Interface 0x5C - 0x6C ECC User Interface 0x70 - 0x7C Reserved 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Name Access EBI_CSA Read/Write – – – Refer to the Static Memory Controller User Interface Refer to the SDRAM Controller User Interface Refer to the Error Code Corrected Controller User interface – ...
Page 158
... NWPC: NWAIT Pin Configuration 0 = The NWAIT device pin is not connected to the External Wait Request input of the Static Memory Controller, this multi- plexed pin can be used as a PIO The NWAIT device pin is connected to the External Wait Request input of the Static Memory Controller. SAM7SE512/256/32 158 – ...
Page 159
... SAM7SE512/256/32 159 ...
Page 160
... SAM7SE512/256/32 160 6222F–ATARM–14-Jan-11 ...
Page 161
... The SMC supports different access protocols allowing single clock cycle memory accesses. It also provides an external wait request capability. 22.2 Block Diagram Figure 22-1. Static Memory Controller Block Diagram Memory Controller 6222F–ATARM–14-Jan-11 SMC SMC Chip Select MCK PMC APB SAM7SE512/256/32 PIO Controller User Interface NCS[7:0] NRD NWR0/NWE NWR1/NUB A0/NLB A[22:1] D[15:0] NWAIT 161 ...
Page 162
... Static Memory Controller Multiplexed Signals Multiplexed Signals Related Function A0 NLB 8-bit or 16-bit data bus, see NWR0 NWE Byte-write or byte-select access, see NWR1 NUB Byte-write or byte-select access, see SAM7SE512/256/32 162 Type Output Output Output Output Output Output Input 22.6.1.3 “Data Bus Width” on page 164. ...
Page 163
... See Figure 22-2. Case of an External Memory Smaller than Page Size 6222F–ATARM–14-Jan-11 1M Byte Device 1M Byte Device Memory Map 1M Byte Device 1M Byte Device SAM7SE512/256/32 Figure 22-2. Base + 4M Bytes Hi Low Base + 3M Bytes Hi Low Base + 2M Bytes ...
Page 164
... A data bus width bits can be selected for each chip select. This option is controlled by the DBW field in the SMC_CSR for the corresponding chip select. See ters” on page Figure 22-4 Figure 22-4. Memory Connection for an 8-bit Data Path Device Figure 22-5 SAM7SE512/256/32 164 (1) NCS2 NCS1 NCS0 196 ...
Page 165
... The signal NRD enables half-word and byte reads. Figure 22-6 6222F–ATARM–14-Jan-11 D[7:0] D[15:8] A[22:1] NLB SMC NUB NWE NRD NCS2 196. shows how to connect two 512K x 8-bit devices in parallel on NCS2 (BAT = 0) SAM7SE512/256/32 D[7:0] D[15:8] A[22:0] Low Byte Enable High Byte Enable Write Enable Output Enable Memory Enable 165 ...
Page 166
... The signal NWR0/NWE is used as NWE and enables writing for byte or half-word. • The signal NRD enables reading for byte or half-word. Figure 22-7 device type) on NCS2 (BAT = 1). Figure 22-7. Connection to a 16-bit Data Path Device with Byte and Half-word Access SAM7SE512/256/32 166 D[7:0] D[15:8] A[22:1] A0 ...
Page 167
... Figure 22-9. Write Access with 0 Wait State A[22:0] D[15:0] 6222F–ATARM–14-Jan-11 shows how to connect a 16-bit device without byte access (e.g., Flash device type) D[7:0] D[15:8] A[19:1] NLB SMC NUB NWE NRD NCS2 Figure 22-9 MCK NCS NWE SAM7SE512/256/32 D[7:0] D[15:8] A[18:0] Write Enable Output Enable Memory Enable and Figure 22-10. 167 ...
Page 168
... During a standard read protocol, NCS is set low and address lines are valid at the beginning of the external memory access, while NRD goes low only in the second half of the master clock cycle to avoid bus conflict. See SAM7SE512/256/32 168 MCK A[22:0] ...
Page 169
... The SMC can automatically insert wait states. The different types of wait states managed are listed below: • Standard wait states • External wait states • Data float wait states • Chip select change wait states • Early Read wait states 6222F–ATARM–14-Jan-11 MCK A[22:0] NCS NRD D[15:0] MCK A[22:0] NCS NRD D[15:0] SAM7SE512/256/32 169 ...
Page 170
... NWS must be programmed as a function of synchronization time and delay between NWAIT fall- ing and control signals falling (NRD/NWE), otherwise SMC will not function correctly. NWS Note: WARNING: If NWAIT is asserted during a setup or hold timing, the SMC does not function correctly. SAM7SE512/256/32 170 (“SMC Chip Select Registers” on page 1 Wait State Access MCK A[22:0] ...
Page 171
... SMC_CSR register for the corresponding chip select on page 6222F–ATARM–14-Jan-11 (2) NWAIT Synchronization Delay NWAIT Synchronization Delay ) for each external memory device is programmed in the TDF DF 196). The value of TDF indicates the number of data float wait cycles (between 0 and SAM7SE512/256/32 (“SMC Chip Select Registers” 171 ...
Page 172
... If a wait state has already been inserted (e.g., data float wait state), then no more wait states are added. SAM7SE512/256/32 172 will not slow down the execution of a program from internal ...
Page 173
... Mem 1 NCS1 NCS2 NRD (1) (2) NWE 1. Early Read Protocol 2. Standard Read Protocol Figure 22-18). This wait state is generated in addition to any other pro- Write Cycle MCK A[22:0] NCS NRD NWE D[15:0] SAM7SE512/256/32 Chip Select Wait Mem 2 addr Mem 2 Early Read Wait Read Cycle 173 ...
Page 174
... Figure 22-19. Read Access with Setup and Hold MCK A[22:0] NRD NRD Setup Figure 22-20. Read Access with Setup SAM7SE512/256/32 174 176 programmed on the first memory bank and when the second DF is higher or equal to the number of setup cycles, the number of setup DF ...
Page 175
... Figure 22-21. Write Access with Setup and Hold MCK A[22:0] NWE D[15:0] NWR Setup Figure 22-22. Write Access with Setup MCK A[22:0] NWE D[15:0] 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Pulse Length NWR Setup Pulse Length NWR Hold NWR Hold 175 ...
Page 176
... Figure 22-23. Consecutive Accesses with Setup Programmed on the Second Access MCK A[22:0] NCS1 NCS2 NWE NRD Figure 22-24. First Access with Data Float Wait States (TDF = 2) and Second Access with Setup (NRDSETUP = 1) MCK A[22:0] NCS1 NCS2 NRD D[15:0] SAM7SE512/256/32 176 Setup Setup Data Float Time 6222F–ATARM–14-Jan-11 ...
Page 177
... Figure 22-25. First Access with Data Float Wait States (TDF = 2) and Second Access with Setup (NRDSETUP = 3) MCK A[22:0] NCS1 NCS2 NRD D[15:0] 6222F–ATARM–14-Jan-11 Setup Data Float Time SAM7SE512/256/32 177 ...
Page 178
... Figure 22-26. Read Access in LCD Interface Mode MCK A[22:0] NRD NCS ACSS Data from LCD Controller Figure 22-27. Write Access in LCD Interface Mode MCK A[22:0] NWE NCS ACCS D[15:0] SAM7SE512/256/32 178 196). ACSS = 3, NWEN = 1, NWS = 10 ACCS = 2, NWEN = 1, NWS = 10 (“SMC Chip ACSS ACCS 6222F–ATARM–14-Jan-11 ...
Page 179
... Read Mem 1 MCK A[22:0] NRD NWE NCS1 NCS2 D[15:0] (Mem 1) D[15:0] (to write) D[15:0] (Mem 2) 6222F–ATARM–14-Jan-11 through Figure 22-31 on page 182 DF Write Mem 1 Read Mem 1 Read Mem 2 Chip Select Change Wait t WHDX SAM7SE512/256/32 show examples of the alternatives Write Mem 2 Read Mem 2 t WHDX 179 ...
Page 180
... Figure 22-29. Early Read Protocol without t Read Mem 1 MCK A[22:0] NRD NWE NCS1 NCS2 D[15:0] (Mem 1) D[15:0] (to write) D[15:0] (Mem 2) SAM7SE512/256/32 180 DF Write Early Read Read Mem 1 Wait Cycle Mem 1 Mem 2 Chip Select Change Wait t WHDX Read Write Early Read Mem 2 Wait Cycle Mem 2 Long t 6222F– ...
Page 181
... Float Wait MCK A[22:0] NRD NWE NCS1 NCS2 D[15:0] (Mem 1) D[15:0] (to write) D[15:0] (Mem 2) 6222F–ATARM–14-Jan-11 DF Write Read Mem 2 Read Mem 1 Data Float Wait WHDX SAM7SE512/256/32 Write Write Mem 2 Mem 2 Read Mem 2 Data Float Wait 181 ...
Page 182
... Figure 22-31. Early Read Protocol with t Write Mem 1 Read Mem 1 Data Float Wait MCK A[22:0] NRD NWE NCS1 NCS2 t DF D[15:0] (Mem 1) D[15:0] (to write) D[15:0] (Mem 2) SAM7SE512/256/32 182 DF Early Read Read Wait Mem 2 Read Mem 1 Data Float Wait t DF Write Write Mem 2 Mem 2 Read Mem 2 Data Float Wait t ...
Page 183
... Write access, memory data bus width = 8, RWSETUP = 1, RWHOLD = 1, WSEN = 1, NWS = 0 6222F–ATARM–14-Jan-11 and Figure 22-33 show an example of read and write accesses with Setup and 00028 Hold 0001 (1) 00082 0605 Hold Setup SAM7SE512/256/32 (1) Setup Hold 0002 0606 Hold 00d2c 008cc 183 ...
Page 184
... MCK NWAIT NWAIT internally synchronized A[22:1] 000008A NRD NWR0/NWE A0/NLB NWR1/NUB NCS D[15:0] 1312 Wait Delay Falling from NWR0/NWE Note: 1. Write access memory, data bus width = 16 bits, WSEN = 1, NWS = 6 SAM7SE512/256/32 184 through Figure 22-37 on page 187 (1) show examples of accesses using 6222F–ATARM–14-Jan-11 ...
Page 185
... Figure 22-35. Write Access using NWAIT in Byte Write Type Access Chip Select Wait MCK NWAIT NWAIT internally synchronized 000008C A[22:1] A0/NLB NRD NWR0/NWE NWR1/NUB NCS D[15:0] Wait Delay Falling from NWR0/NWE/NWR1/NUB Note: 1. Write access memory, data bus width = 16 bits, WSEN = 1, NWS = 5 6222F–ATARM–14-Jan-11 (1) 1716 SAM7SE512/256/32 185 ...
Page 186
... Figure 22-36. Write Access using NWAIT Chip Select Wait MCK NWAIT NWAIT internally synchronized 0000033 A[22:1] A0/NLB NRD NWR0/NWE NWR1/NUB NCS D[15:0] Wait Delay Falling from NWR0/NWE Note: 1. Write access memory, data bus width = 8 bits, WSEN = 1, NWS = 4 SAM7SE512/256/32 186 (1) 0403 6222F–ATARM–14-Jan-11 ...
Page 187
... Figure 22-43 Figure 22-44 6222F–ATARM–14-Jan-11 (1) 0003 through Figure 22-44 on page 194 Table 22-3. Memory Access Waveforms Number of Wait States SAM7SE512/256/32 show the waveforms for read and Bus Width Size of Data Transfer 16 Word 16 Word 16 Half-word 8 Word 8 Half-word 8 Byte 16 Byte 187 ...
Page 188
... Figure 22-38. 0 Wait State, 16-bit Bus Width, Word Transfer MCK A[22:1] NCS NLB NUB Read Access · Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access · Byte Write/ Byte Select Option NWE D[15:0] SAM7SE512/256/32 188 addr+1 addr ...
Page 189
... Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access · Byte Write/ Byte Select Option NWE D[15:0] 6222F–ATARM–14-Jan-11 1 Wait State addr SAM7SE512/256/32 1 Wait State addr 189 ...
Page 190
... Figure 22-40. 1 Wait State, 16-bit Bus Width, Half-Word Transfer MCK A[22:1] NCS NLB NUB Read Access · Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access · Byte Write/ Byte Select Option NWE D[15:0] SAM7SE512/256/32 190 1 Wait State 6222F–ATARM–14-Jan-11 ...
Page 191
... Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access NWR0 NWR1 D[15:0] 6222F–ATARM–14-Jan-11 addr+1 addr SAM7SE512/256/32 addr 191 ...
Page 192
... Figure 22-42. 1 Wait State, 8-bit Bus Width, Half-Word Transfer 1 Wait State MCK A[22:0] NCS Read Access · Standard Read, Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access NWR0 NWR1 D[15:0] SAM7SE512/256/32 192 1 Wait State Addr Addr 6222F–ATARM–14-Jan-11 ...
Page 193
... Figure 22-43. 1 Wait State, 8-bit Bus Width, Byte Transfer MCK A[22:0] NCS Read Access · Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access NWR0 NWR1 D[15:0] 6222F–ATARM–14-Jan-11 1 Wait State SAM7SE512/256/ 193 ...
Page 194
... Standard Read Protocol NRD D[15:0] · Early Read Protocol NRD D[15:0] Write Access · Byte Write Option NWR0 NWR1 D[15:0] · Byte Select Option NWE SAM7SE512/256/32 194 addr addr addr addr ...
Page 195
... SMC Chip Select Register 3 0x10 SMC Chip Select Register 4 0x14 SMC Chip Select Register 5 0x18 SMC Chip Select Register 6 0x1C SMC Chip Select Register 7 6222F–ATARM–14-Jan-11 SAM7SE512/256/32 Table 22-4. Eight Chip Select Registers Name Access SMC_CSR0 Read/Write SMC_CSR1 Read/Write SMC_CSR2 ...
Page 196
... BAT: Byte Access Type This field is used only if DBW defines a 16-bit data bus. 0: Chip select line is connected to two 8-bit wide devices. 1: Chip select line is connected to a 16-bit wide device. SAM7SE512/256/32 196 – ...
Page 197
... Hold Cycles” on page 174 198. SAM7SE512/256/32 (1) (4) RWHOLD NRD Hold cycles cycles cycles ...
Page 198
... Figure 22-45. Read/Write Setup Figure 22-46. Read Hold Figure 22-47. Write Hold SAM7SE512/256/32 198 MCK A[22:0] NRD NWE RWSETUP MCK A[22:0] NRD RWHOLD MCK A[22:0] NWE D[15:0] RWHOLD 6222F–ATARM–14-Jan-11 ...
Page 199
... Block Diagram Figure 23-1. SDRAM Controller Block Diagram 6222F–ATARM–14-Jan-11 SDRAMC SDRAMC Chip Select Memory Controller SDRAMC Interrupt MCK PMC APB SAM7SE512/256/32 PIO Controller User Interface SDCK SDCKE SDCS BA[1:0] RAS CAS SDWE NBS[3:0] A[12:0] D[31:0] 199 ...
Page 200
... Bk[1:0] Bk[1:0] Bk[1:0] Table 23-3. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0] SAM7SE512/256/32 200 Table 23-2 to Table 23-7 illustrate the SDRAM device memory mapping therefore seen CPU Address Line Row[10:0] Row[10:0] Row[10:0] ...