SAM7S64 Atmel Corporation, SAM7S64 Datasheet - Page 83

• Manufacturer Part Number: SAM7S64
• Manufacturer: Atmel Corporation

Specifications of SAM7S64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

3.4.5
3.4.6
3.4.7
ARM DDI 0029G
nTRANS
LOCK
TBIT
The nTRANS output conveys information about the transfer. A MMU can use this
signal to determine whether an access is from a privileged mode or User mode. This
signal can be used with nOPC to implement an access permission scheme. The
meaning of nTRANS is listed in Table 3-5.
More information relevant to the nTRANS signal and security is provided in Privileged
mode access on page 3-32.
LOCK is used to indicate to an arbiter that an atomic operation is being performed on
the bus. LOCK is normally LOW, but is set HIGH to indicate that a SWP or SWPB
instruction is being performed. These instructions perform an atomic read/write
operation, and can be used to implement semaphores.
TBIT is used to indicate the operating state of the ARM7TDMI processor. When in:
•
•
Memory systems do not usually have to use TBIT because MAS[1:0] indicates the size
of the instruction required.
ARM state, the TBIT signal is LOW
Thumb state, the TBIT signal is HIGH.
Note
Copyright © 1994-2001. All rights reserved.
nTRANS
0
1
Table 3-5 nTRANS encoding
Mode
User
Privileged
Memory Interface
3-13