SAM7S64 Atmel Corporation, SAM7S64 Datasheet - Page 163
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SAM7S64
Manufacturer Part Number
SAM7S64
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S64
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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6.14
ARM DDI 0029G
CP
register
status
Single
register
ready
Single
register
not ready
n registers
(n>1)
ready
Coprocessor data transfer from memory to coprocessor
Cycles
1
2
1
2
•
b
b+1
1
2
•
n
n+1
Address
pc+8
alu
pc+12
pc+8
pc+8
pc+8
pc+8
alu
pc+12
pc+8
alu
alu+•
alu+•
alu+•
pc+12
For coprocessor transfer instructions from memory the coprocessor must commit to the
transfer only when it is ready to accept the data. When CPB goes LOW, the processor
produces the addresses and expects the coprocessor to take the data at sequential cycle
rates. The coprocessor is responsible for determining the number of words to be
transferred, and indicates the last transfer cycle by driving CPA and CPB HIGH.
The ARM7TDMI processor spends the first cycle (and any busy-wait cycles) generating
the transfer address, and updates the base address during the transfer cycles.
The cycle timings are listed in Table 6-17 where:
•
•
b represents the busy cycles
n represents the number of registers.
MAS
[1:0]
2
2
2
2
2
2
2
2
2
2
2
2
Copyright © 1994-2001. All rights reserved.
Table 6-17 Coprocessor data transfer instruction cycle operations
nRW
0
0
0
0
0
0
0
0
0
0
0
0
Data
(pc+8)
(alu)
(pc+8)
-
-
-
(alu)
(pc+8)
(alu)
(alu+•)
(alu+•)
(alu+•)
nMREQ
0
0
1
1
1
0
0
0
0
0
0
0
SEQ
0
0
0
0
0
0
0
0
1
1
1
0
nOPC
0
1
0
1
1
1
1
0
1
1
1
1
Instruction Cycle Timings
nCPI
0
1
0
0
0
0
1
0
1
1
1
1
CPA
0
1
0
0
0
0
1
0
0
0
0
1
CPB
0
1
1
1
1
0
1
0
0
0
0
1
6-21
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