SAM7S321 Atmel Corporation, SAM7S321 Datasheet - Page 229
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SAM7S321
Manufacturer Part Number
SAM7S321
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S321
Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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B.5.5
B.5.6
B.5.7
ARM DDI 0029G
CLAMP (0101)
HIGHZ (0111)
CLAMPZ (1001)
This instruction connects a 1 bit shift register, the BYPASS register, between TDI and
TDO. When the CLAMP instruction is loaded into the instruction register, the state of
all the scan cell output signals is defined by the values previously loaded into the
currently loaded scan chain. This instruction must only be used when scan chain 0 is the
currently selected scan chain:
•
•
•
This instruction connects a 1 bit shift register, the BYPASS register, between TDI and
TDO. When the HIGHZ instruction is loaded into the instruction register, the Address
bus, A[31:0], the data bus, D[31:0], nRW, nOPC, LOCK, MAS[1:0], and nTRANS
are all driven to the high impedance state and the external HIGHZ signal is driven
HIGH. This is as if the signal TBE had been driven LOW:
•
•
•
This instruction connects a 1 bit shift register, the BYPASS register, between TDI and
TDO.
When the CLAMPZ instruction is loaded into the instruction register, all the 3-state
outputs are placed in their inactive state, but the data supplied to the scan cell outputs is
derived from the scan cells. The purpose of this instruction is to ensure that, during
production test, each output can be disabled when its data value is either a logic 0 or a
logic 1:
•
•
•
In the CAPTURE-DR state, a logic 0 is captured by the bypass register.
In the SHIFT-DR state, test data is shifted into the bypass register using TDI and
out using TDO after a delay of one TCK cycle. The first bit shifted out is a zero.
In the UPDATE-DR state the bypass register is not affected.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register.
In the SHIFT-DR state, test data is shifted into the bypass register using TDI and
out using TDO after a delay of one TCK cycle. The first bit shifted out is a zero.
In the UPDATE-DR state, the bypass register is not affected.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register.
In the SHIFT-DR state, test data is shifted into the bypass register using TDI and
out using TDO after a delay of one TCK cycle. The first bit shifted out is a zero.
In the UPDATE-DR state, the bypass register is not affected.
Copyright © 1994-2001. All rights reserved.
Debug in Depth
B-11
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