SAM7S321 Atmel Corporation, SAM7S321 Datasheet - Page 101
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SAM7S321
Manufacturer Part Number
SAM7S321
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S321
Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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3.8
ARM DDI 0029G
Action of ARM7TDMI core in debug state
When the ARM7TDMI core is in debug state, nMREQ and SEQ are forced to indicate
internal cycles. This allows the rest of the memory system to ignore the processor and
function as normal. Because the rest of the system continues operation, the core ignores
aborts and interrupts while in debug state.
The BIGEND signal must not be changed by the system during debug. If BIGEND
changes, not only is there a synchronization problem but the programmer view of the
processor changes without the knowledge of the debugger. Signal nRESET must also
be held stable during debug. If nRESET is driven LOW then the state of the processor
changes without the knowledge of the debugger.
When instructions are executed in debug state, all bus interface outputs, except
nMREQ and SEQ, change asynchronously to the memory system. For example, every
time a new instruction is scanned into the pipeline, the address bus changes. Although
this is asynchronous it does not affect the system as nMREQ and SEQ are forced to
indicate internal cycles regardless of what the rest of the processor is doing. The
memory controller must be designed to ensure that this asynchronous behavior does not
affect the rest of the system.
Copyright © 1994-2001. All rights reserved.
Memory Interface
3-31
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