SAM7S256 Atmel Corporation, SAM7S256 Datasheet - Page 238
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SAM7S256
Manufacturer Part Number
SAM7S256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S256
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Debug in Depth
B-20
To access this serial register, scan chain 2 must first be selected using the SCAN_N TAP
controller instruction. The TAP controller must then be placed in INTEST mode.
•
•
•
Scan chain 3
Purpose
Length
Scan chain 3 control signals are provided so that an optional external boundary-scan
chain can be controlled through the ARM7TDMI core. Typically, this is used for a scan
chain around the pad ring of a packaged device.
The following control signals are provided which are generated only when scan chain
3 has been selected. These outputs are inactive at all other times:
DRIVEBS
PCLKBS
ICAPCLKBS, ECAPCLKBS
SHCLKBS, SHCLK2BS
During CAPTURE-DR, no action is taken.
During SHIFT-DR, a data value is shifted into the serial register. Bits 32 to 36
specify the address of the EmbeddedICE Logic register to be accessed.
During UPDATE-DR, this register is either read or written depending on the value
of bit 37, with 0=read).
Copyright © 1994-2001. All rights reserved.
Enables the ARM7TDMI core to control an external boundary-scan
chain.
User defined.
This is used to switch the scan cells from system mode to test mode. This
signal is asserted whenever either the INTEST, EXTEST, CLAMP, or
CLAMPZ instruction is selected.
This is an update clock, generated in the UPDATE-DR state. Typically
the value scanned into a chain is transferred to the cell output on the rising
edge of this signal.
These are capture clocks used to sample data into the scan cells during
INTEST and EXTEST respectively. These clocks are generated in the
CAPTURE-DR state.
These are non-overlapping clocks generated in the SHIFT-DR state used
to clock the master and slave element of the scan cells respectively. When
the state machine is not in the SHIFT-DR state, both these clocks are
LOW.
ARM DDI 0029G
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