SAM7S256 Atmel Corporation, SAM7S256 Datasheet - Page 131
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SAM7S256
Manufacturer Part Number
SAM7S256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S256
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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5.3.2
ARM DDI 0029G
Action of the processor in debug state
When the ARM7TDMI core enters debug state, the core forces nMREQ and SEQ to
indicate internal cycles. This action allows the rest of the memory system to ignore the
core and to function as normal. Because the rest of the system continues to operate, the
ARM7TDMI is forced to ignore aborts and interrupts.
The system must not change the BIGEND signal during debug because the debugger is
unaware that the core has been reconfigured.
nRESET must be held stable during debug because resetting the core while debugging
causes the debugger to lose track of the core.
When the system applies reset to the ARM7TDMI processor, with nRESET driven
LOW, the processor state changes with the debugger unaware that the core has reset.
When instructions are executed in debug state, all memory interface outputs, except
nMREQ and SEQ, change asynchronously to the memory system. For example, every
time a new instruction is scanned into the pipeline, the address bus changes. Although
this is asynchronous it does not affect the system, as nMREQ and SEQ are forced to
indicate internal cycles regardless of what the rest of the core is doing. The memory
controller must be designed to ensure that this asynchronous behavior does not affect
the rest of the system.
Copyright © 1994-2001. All rights reserved.
Debug Interface
5-9
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