SAM7S128 Atmel Corporation, SAM7S128 Datasheet
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
SAM7S128
Specifications of SAM7S128
Related parts for SAM7S128
SAM7S128 Summary of contents
Page 1
... Bytes (Dual Plane) – 256 Kbytes (SAM7S256) Organized in 1024 Pages of 256 Bytes (Single Plane) – 128 Kbytes (SAM7S128) Organized in 512 Pages of 256 Bytes (Single Plane) – 64 Kbytes (SAM7S64) Organized in 512 Pages of 128 Bytes (Single Plane) – 32 Kbytes (SAM7S321/32) Organized in 256 Pages of 128 Bytes (Single Plane) – ...
Page 2
Counter May Be Stopped While the Processor is in Debug State or in Idle Mode • Real-time Timer (RTT) – 32-bit Free-running Counter with Alarm – Runs Off the Internal RC Oscillator • One Parallel Input/Output Controller (PIOA) – ...
Page 3
... Their aggressive price point and high level of integration pushes their scope of use far into the cost-sensitive, high-volume consumer market. 1.1 Configuration Summary of the SAM7S512, SAM7S256, SAM7S128, SAM7S64, SAM7S321, SAM7S32, SAM7S161 and SAM7S16 The SAM7S512, SAM7S256, SAM7S128, SAM7S64, SAM7S321, SAM7S32, SAM7S161 and SAM7S16 differ in memory size, peripheral set and package ...
Page 4
Block Diagram Figure 2-1. SAM7S512/256/128/64/321/161 Block Diagram TDI TDO JTAG TMS SCAN TCK JTAGSEL System Controller TST FIQ IRQ0-IRQ1 PCK0-PCK2 PLLRC PLL XIN OSC XOUT RCOSC VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 ...
Page 5
Figure 2-2. SAM7S32/16 Block Diagram TDI TDO TMS TCK JTAGSEL System Controller TST FIQ IRQ0 PCK0-PCK2 PLLRC PLL XIN OSC XOUT VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK ...
Page 6
Signal Description Table 3-1. Signal Description List Signal Name Function Voltage and ADC Regulator Power Supply VDDIN Input VDDOUT Voltage Regulator Output VDDFLASH Flash Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL GND Ground ...
Page 7
Table 3-1. Signal Description List (Continued) Signal Name Function DDM USB Device Port Data - DDP USB Device Port Data + SCK0 - SCK1 Serial Clock TXD0 - TXD1 Transmit Data RXD0 - RXD1 Receive Data RTS0 - RTS1 Request ...
Page 8
Table 3-1. Signal Description List (Continued) Signal Name Function TWD Two-wire Serial Data TWCK Two-wire Serial Clock AD0-AD3 Analog Inputs AD4-AD7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN2 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming ...
Page 9
Package and Pinout The SAM7S512/256/128/64/321 are available in a 64-lead LQFP or 64-pad QFN package. The SAM7S161 is available in a 64-Lead LQFP package. The SAM7S32/16 are available in a 48-lead LQFP or 48-pad QFN package. 4.1 64-lead LQFP ...
Page 10
LQFP and 64-pad QFN Pinout Table 4-1. SAM7S512/256/128/64/321/161 Pinout 1 ADVREF 17 2 GND 18 3 AD4 19 4 AD5 20 5 AD6 21 6 AD7 22 7 VDDIN 23 8 VDDOUT 24 9 PA17/PGMD5/AD0 25 10 PA18/PGMD6/AD1 ...
Page 11
LQFP and 48-pad QFN Package Outlines Figure 4-3 age. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet. Figure 4-3. Figure 4-4. 4.4 48-lead LQFP and 48-pad QFN Pinout Table 4-2. SAM7S32/16 ...
Page 12
Power Considerations 5.1 Power Supplies The SAM7S Series has six types of power supply pins and integrates a voltage regulator, allow- ing the device to be supplied with only one voltage. The six power supply pin types are: • ...
Page 13
Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 ...
Page 14
I/O Lines Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven ...
Page 15
I/O line to VDDIO. Care should be taken, in particular at reset, as all the I/O lines default to input with the pull-up resistor enabled at reset. 6.6 I/O Line Drive Levels The PIO lines PA0 to ...
Page 16
Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM – Thumb • Three-stage pipeline architecture – Instruction ...
Page 17
Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and locking operations – Interrupt generation in case of forbidden operation 7.4 Peripheral DMA Controller ...
Page 18
... Protection Mode to secure contents of the Flash • 64 Kbytes of Fast SRAM – Single-cycle access at full speed 8.3 SAM7S128 • 128 Kbytes of Flash Memory, single plane – 512 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – ...
Page 19
SAM7S64 • 64 Kbytes of Flash Memory, single plane – 512 pages of 128 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – Page programming ...
Page 20
Figure 8-1. SAM SAM7S512/256/128/64/321/32/161/16 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256M Bytes 0xFFFF FFFF SAM7S Series Summary ...
Page 21
... The SAM7S512 features two contiguous banks (dual plane) of 256 Kbytes of Flash. • The SAM7S256 features one bank (single plane) of 256 Kbytes of Flash. • The SAM7S128 features one bank (single plane) of 128 Kbytes of Flash. • The SAM7S64 features one bank (single plane Kbytes of Flash. ...
Page 22
... The Flash of the SAM7S256 is organized in 1024 pages (single plane) of 256 bytes. The 262,144 bytes are organized in 32-bit words. • The Flash of the SAM7S128 is organized in 512 pages (single plane) of 256 bytes. The 131,072 bytes are organized in 32-bit words. • The Flash of the SAM7S64 is organized in 512 pages (single plane) of 128 bytes. The 65,536 bytes are organized in 32-bit words. • ...
Page 23
... SAM7S128 The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The SAM7S128 contains 8 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes locked-region’s erase or program command occurs, the command is aborted and the LOCKE bit in the MC_FSR register rises and the interrupt line rises if the LOCKE bit has been written the MC_FMR register ...
Page 24
... Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. Table 8-1 Table 8-1. Flash Configuration Summary Device Number of Lock Bits SAM7S512 32 SAM7S256 16 SAM7S128 8 SAM7S64 16 SAM7S321/32 8 SAM7S161/16 8 8.8.4 Security Bit Feature The SAM7S Series features a security bit, based on a specific NVM Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Pro- gramming Interface, is forbidden ...
Page 25
This security bit can only be enabled, through the Command “Set Security Bit” of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is ...
Page 26
Communication through the USB Device Port is limited to an 18.432 MHz crystal. ( The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). 9. System Controller The System Controller manages all vital blocks of the microcontroller: ...
Page 27
Figure 9-1. System Controller Block Diagram (SAM7S512/256/128/64/321/161) NRST XIN XOUT PLLRC PA0-PA31 6175JS–ATARM–28-Jul-11 wdt_irq dbgu_irq pmc_irq rstc_irq MCK Debug periph_nreset Unit dbgu_rxd Periodic MCK debug Interval periph_nreset Timer SLCK Real-Time Timer periph_nreset SLCK Watchdog debug idle Timer proc_nreset cal gpnvm[1] ...
Page 28
Figure 9-2. System Controller Block Diagram (SAM7S32/16) periph_irq[2..14] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset periph_nreset en BOD POR NRST RCOSC XIN OSC XOUT PLL PLLRC periph_nreset periph_nreset periph_clk[2] PA0-PA20 SAM7S Series Summary 28 Interrupt Controller MCK Debug Unit ...
Page 29
Reset Controller The Reset Controller is based on a power-on reset cell and one brownout detector. It gives the status of the last reset, indicating whether power-up reset, a software reset, a user reset, a watchdog ...
Page 30
Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 kHz and 42 kHz • Main Oscillator frequency ranges between 3 and 20 ...
Page 31
Figure 9-4. 9.4 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ ARM Processor • Individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is ...
Page 32
... Chip ID is 0x270B0942 for AT91SAM7S256 Rev C – Chip ID is 0x270C0740 for AT91SAM7S128 Rev A – Chip ID is 0x270A0741 for AT91SAM7S128 Rev B – Chip ID is 0x270A0742 for AT91SAM7S128 Rev C – Chip ID is 0x27090540 for AT91SAM7S64 Rev A – Chip ID is 0x27090543 for AT91SAM7S64 Rev B – ...
Page 33
Real-time Timer • 32-bit free-running counter with alarm running on prescaled SCLK • Programmable 16-bit prescaler for SLCK accuracy compensation 9.9 PIO Controller • One PIO Controller, controlling 32 I/O lines (21 for SAM7S32/16) • Fully programmable through set/clear ...
Page 34
Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 MBytes of address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in 10.2 ...
Page 35
Table 10-2. Peripheral Note: 10.3 Peripheral Multiplexing on PIO Lines The SAM7S Series features one PIO controller, PIOA, that ...
Page 36
PIO Controller A Multiplexing Table 10-3. Multiplexing on PIO Controller A (SAM7S512/256/128/64/321/161) PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD ...
Page 37
Table 10-4. Multiplexing on PIO Controller A (SAM7S32/16) PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD PA10 DTXD PA11 NPCS0 PA12 ...
Page 38
Serial Peripheral Interface • Supports communication with external serial devices – Four chip selects with external decoder allow communication with – Serial memories, such as DataFlash – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN ...
Page 39
ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication 115.2 Kbps • Test Modes ...
Page 40
PWM Controller • Four channels, one 16-bit counter per channel • Common clock generator, providing thirteen different clocks – One Modulo n counter providing eleven clocks – Two independent linear dividers working on modulo n counter outputs • Independent ...
Page 41
Package Drawings The SAM7S series devices are available in LQFP and QFN package types. 11.1 LQFP Packages Figure 11-1. 48-and 64-lead LQFP Package Drawing 6175JS–ATARM–28-Jul-11 SAM7S Series Summary 41 ...
Page 42
Table 11-1. Symbol θ 1 θ 2 θ aaa bbb ccc ddd SAM7S Series Summary 42 48-lead LQFP Package Dimensions (in ...
Page 43
Table 11-2. Symbol θ θ θ aaa bbb ccc ddd 6175JS–ATARM–28-Jul-11 64-lead LQFP Package Dimensions (in mm) Millimeter Min Nom – – ...
Page 44
QFN Packages Figure 11-2. 48-pad QFN Package SAM7S Series Summary 44 6175JS–ATARM–28-Jul-11 ...
Page 45
Table 11-3. Symbol aaa bbb ccc 6175JS–ATARM–28-Jul-11 48-pad QFN Package Dimensions (in mm) Millimeter Min Nom Max – – 090 – – 0.050 – 0.65 0.70 0.20 REF ...
Page 46
Figure 11-3. 64-pad QFN Package Drawing ll dimensions are in mm eference : JEDEC Drawing MO-220 SAM7S Series Summary 46 6175JS–ATARM–28-Jul-11 ...
Page 47
Table 11-4. Symbol aaa bbb ccc 6175JS–ATARM–28-Jul-11 64-pad QFN Package Dimensions (in mm) Millimeter Min Nom Max – – 090 – – 0.05 – 0.65 0.70 0.20 REF ...
Page 48
... AT91SAM7S512-AU AT91SAM7S512B-AU AT91SAM7S512-MU AT91SAM7S512B-MU SAM7S Series Summary 48 MLR C Ordering Code – – – – – – – AT91SAM7S64C-AU AT91SAM7S64C-MU AT91SAM7S128C-AU AT91SAM7S128C-MU AT91SAM7S256C-AU AT91SAM7S256C-MU – Package Temperature Package Type Operating Range LQFP 48 Industrial Green (-40⋅ 85⋅ C) QFN 48 Industrial LQFP 64 Green (-40⋅ 85⋅ C) ...
Page 49
Revision History Doc. Rev Comments First issue - Unqualified on Intranet 6175AS Corresponds to 6175A full datasheet approval loop. Qualified on Intranet. 6175BS Section 8. “Memories” on page 18 6175CS Section 12. ”SAM7S Ordering Information” “Features”, Table 1-1, “Configuration Summary,” ...
Page 50
Doc. Rev Comments 6175GS “Features”,“Debug Unit (DBGU)” Communication” Section 7.4 ”Peripheral DMA Section 9. ”System Controller”, Section 9.1.1 ”Brownout Detector and Power-on Section 9.5 ”Debug Unit”, the list; B and SAM7S64 Rev B to the list. Section 12. ”SAM7S Ordering ...
Page 51
... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2011 Atmel Corporation. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. ARM or trademarks of ARM Limited. Other terms and product names may be the trademarks of others. International ...