SAM3N2C Atmel Corporation, SAM3N2C Datasheet - Page 18

• Manufacturer Part Number: SAM3N2C
• Manufacturer: Atmel Corporation

Specifications of SAM3N2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 47
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.4
5.5
5.5.1
18
Active Mode
Low Power Modes
SAM3N
Backup Mode
Figure 5-3.
Active mode is the normal running mode with the core clock running from the fast RC oscillator,
the main crystal oscillator or the PLL. The power management controller can be used to adapt
the frequency and to disable the peripheral clocks.
The various low-power modes of the SAM3N are described below:
The purpose of backup mode is to achieve the lowest power consumption possible in a system
that is performing periodic wakeups to carry out tasks but not requiring fast startup time
(<0.1ms). Total current consumption is 3 µA typical.
The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz
oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The
regulator and the core supply are off.
Backup mode is based on the Cortex-M3 deep sleep mode with the voltage regulator disabled.
The SAM3N can be awakened from this mode through WUP0-15 pins, the supply monitor (SM),
the RTT or RTC wake-up event.
Backup mode is entered by using WFE instructions with the SLEEPDEEP bit in the System Con-
trol Register of the Cortex-M3 set to 1. (See the “Power Management” description in The ARM
Cortex M3 Processor section of the product datasheet).
Exit from Backup mode happens if one of the following enable wake-up events occurs:
• WKUPEN0-15 pins (level transition, configurable debouncing)
Main Supply
Core Externally Supplied (backup battery)
Backup
Battery
IN
ON/OFF
3.3V
LDO
Note: The two diodes provide a “switchover circuit” (for illustration purpose)
between the backup battery and the main supply when the system is put in
backup mode.
+
-
OUT
External wakeup signal
ADC, DAC Supply
(3V-3.6V)
VDDCORE
VDDIO
VDDPLL
VDDOUT
VDDIN
PIOx (Output)
WAKEUPx
Regulator
ADC, DAC
Voltage
I/Os.
11011A–ATARM–04-Oct-10