SAM3N1C Atmel Corporation, SAM3N1C Datasheet - Page 262
SAM3N1C
Manufacturer Part Number
SAM3N1C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N1C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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16.4.6
16.4.6.1
16.4.6.2
16.4.7
262
262
SAM3N
SAM3N
Core Reset
Wake Up Sources
Supply Monitor Reset
Brownout Detector Reset
The Supply Controller manages the vddcore_nreset signal to the Reset Controller, as described
previously in
asserted before shutting down the core power supply and released as soon as the core power
supply is correctly regulated.
There are two additional sources which can be programmed to activate vddcore_nreset:
The supply monitor is capable of generating a reset of the system. This can be enabled by set-
ting the SMRSTEN bit in the Supply Controller Supply Monitor Mode Register (SUPC_SMMR).
If SMRSTEN is set and if a supply monitor detection occurs, the vddcore_nreset signal is imme-
diately activated for a minimum of 1 slow clock cycle.
The brownout detector provides the bodcore_in signal to the SUPC which indicates that the volt-
age regulation is operating as programmed. If this signal is lost for longer than 1 slow clock
period while the voltage regulator is enabled, the Supply Controller can assert vddcore_nreset.
This feature is enabled by writing the bit, BODRSTEN (Brownout Detector Reset Enable) to 1 in
the Supply Controller Mode Register (SUPC_MR).
If BODRSTEN is set and the voltage regulation is lost (output voltage of the regulator too low),
the vddcore_nreset signal is asserted for a minimum of 1 slow clock cycle and then released if
bodcore_in has been reactivated. The BODRSTS bit is set in the Supply Controller Status Reg-
ister (SUPC_SR) so that the user can know the source of the last reset.
Until bodcore_in is deactivated, the vddcore_nreset signal remains active.
The wake up events allow the device to exit backup mode. When a wake up event is detected,
the Supply Controller performs a sequence which automatically reenables the core power
supply.
• a supply monitor detection
• a brownout detection
Section 16.4.5 ”Power Supply
Reset”. The vddcore_nreset signal is normally
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
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