SAM3N1A Atmel Corporation, SAM3N1A Datasheet - Page 632
SAM3N1A
Manufacturer Part Number
SAM3N1A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N1A
Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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32.6.2.2
632
SAM3N
Waveform Properties
The different properties of output waveforms are:
• the internal clock selection. The internal channel counter is clocked by one of the clocks
• the waveform period. This channel parameter is defined in the CPRD field of the
• the waveform duty cycle. This channel parameter is defined in the CDTY field of the
• the waveform polarity. At the beginning of the period, the signal can be at high or low level.
provided by the clock generator described in the previous section. This channel parameter is
defined in the CPRE field of the PWM_CMRx register. This field is reset at 0.
PWM_CPRDx register.
- If the waveform is left aligned, then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula
will be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
PWM_CDTYx register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
This property is defined in the CPOL field of the PWM_CMRx register. By default the signal
starts by a low level.
(
------------------------------- -
(
--------------------------------------------- -
(
------------------------------------------ -
(
--------------------------------------------------- -
X
X*CPRD*DIVA
2
2*X*CPRD*DIVA
duty cycle
duty cycle
×
×
MCK
X
CPRD
MCK
MCK
×
MCK
CPRD
)
=
=
)
(
----------------------------------------------------------------------------------------------------------- -
)
(
----------------------------------------------------------------------------------------------------------------------------- -
period 1
(
or
period
)
or
(
--------------------------------------------- -
X*CPRD*DIVB
(
--------------------------------------------------- -
2*X*CPRD*DIVB
–
⁄
MCK
2
⁄
) 1
MCK
fchannel_x_clock
–
period
⁄
(
period
)
fchannel_x_clock
)
⁄
2
)
×
CDTY
×
CDTY
)
) )
11011A–ATARM–04-Oct-10
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