RM9200 Atmel Corporation, RM9200 Datasheet - Page 22

• Manufacturer Part Number: RM9200
• Manufacturer: Atmel Corporation

Specifications of RM9200

• Flash (kbytes): 0 Kbytes
• Pin Count: 256
• Max. Operating Frequency: 180 MHz
• Cpu: ARM920
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 122
• Ext Interrupts: 122
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 1
• Twi (i2c): 1
• Uart: 5
• Ssc: 3
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

10.3
22
Peripheral Multiplexing on PIO Lines
AT91RM9200
Table 10-1.
The AT91RM9200 features four PIO controllers:
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral
functions, A or B. The tables in the following paragraphs define how the I/O lines of the peripher-
als A and B are multiplexed on the PIO Controllers A, B, C and D. The two columns “Function”
and “Comments” have been inserted for the user’s own comments; they may be used to track
how pins are defined in an application.
The column “Reset State” indicates whether the PIO line resets in I/O mode or in peripheral
mode. If equal to “I/O”, the PIO line resets in input with the pull-up enabled so that the device is
maintained in a static state as soon as the NRST pin is asserted. As a result, the bit correspond-
ing to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is in the “Reset State” column, the PIO line is assigned to this function and the
corresponding bit in PIO_PSR resets high. This is the case for pins controlling memories, either
address lines or chip selects, and that require the pin to be driven as soon as NRST raises. Note
that the pull-up resistor is also enabled in this case.
See
page
Peripheral
ID
24
25
26
27
28
29
30
31
• PIOA and PIOB, multiplexing I/O lines of the peripheral set
• PIOC, multiplexing the data bus bits 16 to 31 and several External Bus Interface control
• PIOD, available in the 256-ball BGA package option only, multiplexing outputs of the
signals. Using PIOC pins increases the number of general-purpose I/O lines available but
prevents 32-bit memory access
peripheral set and the ETM port
Table 10-2 on page
26.
Peripheral Identifiers (Continued)
Peripheral
Mnemonic
EMAC
AIC
AIC
AIC
AIC
AIC
AIC
AIC
23,
Table 10-3 on page
Peripheral
Name
Ethernet MAC
Advanced Interrupt Controller
Advanced Interrupt Controller
Advanced Interrupt Controller
Advanced Interrupt Controller
Advanced Interrupt Controller
Advanced Interrupt Controller
Advanced Interrupt Controller
24,
Table 10-4 on page 25
1768MS–ATARM–09-Jul-09
and
External
Interrupt
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
Table 10-5 on