ATxmega64D4 Atmel Corporation, ATxmega64D4 Datasheet - Page 140

• Manufacturer Part Number: ATxmega64D4
• Manufacturer: Atmel Corporation

Specifications of ATxmega64D4

• Flash (kbytes): 64 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Speed: No
• Usb Interface: No
• Spi: 4
• Twi (i2c): 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 14
• Input Capture Channels: 14
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.11.5
12.11.6
8210B–AVR–04/10
CTRLE - Control Register E
INTCTRLA - Interrupt Enable Register A
Table 12-5.
• Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 - BYTEM: Byte Mode:
Enabling the Byte Mode, sets the Timer/Counter in Byte (8-bit) Mode. Setting this bit will disable
the update of the temporary register (TEMP) when any of the 16-bit Timer/Counter registers are
accessed. In addition the upper byte of the counter (CNT) register will be set to zero after each
counter clock.
• Bit 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
EVSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
Timer Event Source Selection
7
–
R
0
R
7
–
0
Group Configuration
R
6
–
0
R
6
–
0
OFF
CHn
R
5
–
0
R
5
–
0
Event Source
None
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Event channel n, n={0,...,3}
R
4
–
0
R
4
–
0
R/W
3
–
R
0
3
ERRINTLVL[1:0]
0
R/W
R
2
–
0
2
0
R/W
R
1
–
0
1
OVFINTLVL[1:0]
0
XMEGA D
BYTEM
R/W
R/W
0
0
0
0
INTCTRLA
CTRLE
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