ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 100

• Manufacturer Part Number: ATxmega64A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A1

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

35.2
8067M–AVR–09/10
ATxmega128A1 rev. G
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1. Bootloader Section in Flash is non-functional
2. Bandgap voltage input for the ACs cannot be changed when used for both ACs
3. DAC is nonlinear and inaccurate when reference is above 2.4V
Bootloader Section in Flash is non-functional
Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
DAC is nonlinear and inaccurate when reference is above 2.4V
ADC gain stage output range is limited to 2.4 V
The ADC has up to ±2 LSB inaccuracy
TWI, a general address call will match independent of the R/W-bit value
TWI, the minimum I
Setting HIRES PR bit makes PWM output unavailable
EEPROM erase and write does not work with all System Clock sources
BOD will be enabled after any reset
Propagation delay analog Comparator increasing to 2 ms at -40°C
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Default setting for SDRAM refresh period too low
Flash Power Reduction Mode can not be enabled when entering sleep mode
Enabling Analog Comparator B output will cause JTAG failure
JTAG enable does not override Analog Comparator B output
Bandgap measurement with the ADC is non-functional when V
DAC refresh may be blocked in S/H mode
Inverted I/O enable does not affect Analog Comparator Output
Both DFLLs and both oscillators has to be enabled for one to work
The Bootloader Section is non-functional, and bootloader or application code cannot reside
in this part of the Flash.
Problem fix/Workaround
None, do not use the Bootloader Section.
simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then
selected/deselected as input for the another AC, the first comparator will be affected for up
to 1 us and could potentially give a wrong comparison result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both
ACs before enabling any of them.
Using the DAC with a reference voltage above 2.4V give inaccurate output when converting
codes that give below 0.75V output:
– ±20 LSB for continuous mode
– ±200 LSB for Sample and Hold mode
Problem fix/Workaround
None, avoid using a voltage reference above 2.4V.
2
C SCL low time could be violated in Master Read mode
CC
is below 2.7V
XMEGA A1
100