ATxmega128A3 Atmel Corporation, ATxmega128A3 Datasheet - Page 108

• Manufacturer Part Number: ATxmega128A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A3

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8068T–AVR–12/10
4. Flash Power Reduction Mode can not be enabled when entering sleep mode
5. JTAG enable does not override Analog Comparator B output
6. Bandgap measurement with the ADC is non-functional when V
7. DAC refresh may be blocked in S/H mode
8. BOD will be enabled after any reset
9. Both DFLLs and both oscillators has to be enabled for one to work
If Flash Power Reduction Mode is enabled when a deep sleep mode, the device will only
wake up on every fourth wake-up request.
If Flash Power Reduction Mode is enabled when entering Idle sleep mode, the wake-up time
will vary with up to 16 CPU clock cycles.
Problem fix/Workaround
Disable Flash Power Reduction mode before entering sleep mode.
When JTAG is enabled this will not override the Anlog Comparator B (ACB)ouput, AC0OUT
on pin 7 if this is enabled.
Problem fix/Workaround
AC0OUT for ACB should not be enabled when JTAG is used. Use only analog comparator
output for ACA when JTAG is used, or use the PDI as debug interface.
The ADC cannot be used to do bandgap measurements when V
Problem fix/Workaround
If internal voltages must be measured when V
reference instead of the bandgap.
If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is
done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this
will block refresh signals to the second channel.
Problem fix/Workarund
When using the DAC in S/H mode, ensure that none of the channels is running at maximum
conversion rate, or ensure that the conversion rate of both channels is high enough to not
require refresh.
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
In order to use the automatic runtime calibration for the 2 MHz or the 32MHz internal oscilla-
tors, the DFLL for both oscillators and both oscillators has to be enabled for one to work.
Problem fix/Workaround
Enable both the DFLLs and both oscillators when using automatic runtime calibration for
one of the internal oscillators.
CC
is below 2.7V, measure the internal 1.00V
CC
CC
is below 2.7V.
is below 2.7V
XMEGA A3
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