ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 893
ATUC64L4U
Manufacturer Part Number
ATUC64L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC64L4U
Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATUC64L4U-D3HR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATUC64L4U-H
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATUC64L4U-U
Manufacturer:
ATMEL
Quantity:
20
Part Number:
ATUC64L4U-ZUT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
- Current page: 893 of 960
- Download datasheet (15Mb)
34.6.8.5
34.6.8.6
34.6.8.7
Table 34-56. STATUS_INFO Contents
32142A–12/2011
Bit number
15-9
4-1
8
7
6
5
0
MEMORY_READWRITE_STATUS
BAUD_RATE
STATUS_INFO
Name
Reserved
Reserved
Protected
SAB busy
Chip erase ongoing
CPU halted
Reset status
After a MEMORY_WRITE command this response is sent by AW. The response can also be
sent after a MEMORY_READ command if AW encountered an error when receiving the
address. The response contains 3 bytes, where the first is the status of the command and the 2
next contains the byte count when the first error occurred. The first byte is encoded this way:
Table 34-53. MEMORY_READWRITE_STATUS Status Byte
Table 34-54. MEMORY_READWRITE_STATUS Details
The current baud rate in the AW. See
Table 34-55. BAUD_RATE Details
A status message from AW.
status byte
0x00
0x01
0x02
Other
Response
Response value
Additional data
Response
Response value
Additional data
Description
The protection bit in the internal flash is set. SAB access is restricted. This bit
will read as one during reset.
The SAB bus is busy with a previous transfer. This could indicate that the CPU
is running on a very slow clock, the CPU clock has stopped for some reason
or that the part is in constant reset.
The Chip erase operation has not finished.
This bit will be set if the CPU is halted. This bit will read as zero during reset.
This bit will be set if AW has reset the CPU using the RESET command.
Description
Write successful
SAB busy
Bus error (wrong address)
Reserved
Details
0xC2
Status byte and byte count (2 bytes)
Details
0xC3
Baud rate
Section 34.6.6.7
ATUC64/128/256L3/4U
for more details.
893
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