ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 794

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

31.7.12
Name:
Access Type:
Offset:
Reset Value:
• ACCTRL: Analog Comparator Control
• CONSEN: Consensus Filter Length
• CXDILEN: Cx Capacitor Discharge Length
• SYNCTIM: Sync Time Interval
32142A–12/2011
ACCTRL
31
23
15
7
When written to one, allows the CAT to disable the analog comparators when they are not needed. When written to zero, the
analog comparators are always enabled.
For QMatrix sensors, specifies that discharge will be terminated when CONSEN out of the most recent 5 comparator samples
are positive. For example, a value of 3 in the CONSEN field will terminate discharge when 3 out of the most recent 5 comparator
samples are positive. When CONSEN has the default value of 0, discharge will be terminated immediately when the comparator
output goes positive.
For QMatrix sensors, specifies how many burst prescaler clock cycles the CAT should use to discharge the Cx capacitor at the
end of each burst cycle.
When non-zero, determines the number of prescaled clock cycles between the start of the acquisition on each X line for QMatrix
acquisition.
Matrix Group Configuration Register 2
30
22
14
6
MGCFG2
Read/Write
0x38
0x00000000
-
CONSEN
29
21
13
5
28
20
12
4
SYNCTIM[7:0]
CXDILEN
27
19
11
3
ATUC64/128/256L3/4U
26
18
10
2
SYNCTIM[11:8]
-
25
17
9
1
24
16
8
0
794