ATmega649A Atmel Corporation, ATmega649A Datasheet - Page 61
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ATmega649A
Manufacturer Part Number
ATmega649A
Description
Manufacturer
Atmel Corporation
Specifications of ATmega649A
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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13. External Interrupts
13.1
8284D–AVR–6/11
Overview
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
The External Interrupts are triggered by the INT0 pin or any of the PCINT30:0 pins
that, if enabled, the interrupts will trigger even if the INT0 or PCINT30:0 pins are configured as
outputs. This feature provides a way of generating a software interrupt. The pin change interrupt
PCI1 will trigger if any enabled PCINT15:8 pin toggles. Pin change interrupts PCI0 will trigger if
any enabled PCINT7:0 pin toggles. The PCMSK3
isters control which pins contribute to the pin change interrupts. Pin change interrupts on
PCINT30:0 are detected asynchronously. This implies that these interrupts can be used for wak-
ing the part also from sleep modes other than Idle mode.
The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as
indicated in the specification for the
When the INT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger
as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0
requires the presence of an I/O clock, described in
page
can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is
halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in
Notes:
”System Clock and Clock Options” on page
30. Low level interrupt on INT0 is detected asynchronously. This implies that this interrupt
1. PCMSK3 and PCMSK2 are only present in ATmega3290A/3290PA/6490A/6490P.
2. PCINT30:16 are only present in ATmega3290A/3290PA/6490A/6490P. Only PCINT15:0 are
present in ATmega169A/169PA; ATmega329A/329PA and ATmega649A/649P. See
figurations” on page 2
and
”Register Description” on page 62
”EICRA – External Interrupt Control Register A” on page
30.
(1)
, PCMSK2
”Clock Systems and their Distribution” on
(1)
, PCMSK1, and PCMSK0 Reg-
for details.
(2)
. Observe
”Pin Con-
62.
61
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