ATmega649A Atmel Corporation, ATmega649A Datasheet - Page 303
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ATmega649A
Manufacturer Part Number
ATmega649A
Description
Manufacturer
Atmel Corporation
Specifications of ATmega649A
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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27.8.10
27.8.11
8284D–AVR–6/11
Preventing Flash Corruption
Programming Time for Flash when Using SPM
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below.
Refer to
When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction
is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the
value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below.
Refer to
byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
During periods of low V
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock
2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
3. Keep the AVR core in Power-down sleep mode during periods of low V
The calibrated RC Oscillator is used to time Flash accesses.
gramming time for Flash accesses from the CPU.
Table 27-5.
Note:
Bit
Rd
Bit
Rd
Flash write (Page Erase, Page Write, and
write Lock bits by SPM)
bits to prevent any Boot Loader software updates.
This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-
age matches the detection level. If not, an external low V
used. If a reset occurs while a write operation is in progress, the write operation will be
completed provided that the power supply voltage is sufficient.
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
1. Minimum and maximum programming time is per individual operation.
Table 28-4 on page 312
Table 28-3 on page 311
SPM Programming Time
FHB7
Symbol
7
7
–
CC
FHB6
, the Flash program can be corrupted because the supply voltage is
6
6
–
for detailed description and mapping of the Fuse High byte.
FHB5
for detailed description and mapping of the Extended Fuse
5
5
–
Min Programming Time
FHB4
4
4
–
3.7ms
FHB3
3
3
–
CC
Table 27-5
FHB2
EFB2
reset protection circuit can be
2
2
Max Programming Time
FHB1
EFB1
1
1
shows the typical pro-
CC
. This will pre-
4.5ms
FHB0
EFB0
0
0
303
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