ATmega48 Automotive Atmel Corporation, ATmega48 Automotive Datasheet - Page 31
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ATmega48 Automotive
Manufacturer Part Number
ATmega48 Automotive
Description
Manufacturer
Atmel Corporation
Specifications of ATmega48 Automotive
Flash (kbytes)
4 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
256
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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7.8
7.9
7.9.1
7701E–AVR–02/11
128kHz Internal Oscillator
System Clock Prescaler
Switching Time
The 128kHz internal oscillator is a low power oscillator providing a 128kHz clock. The fre-
quency is nominal at 3V and 25°C. This clock may be selected as the system clock by
programming the CKSEL fuses to "0100".
When this clock source is selected, start-up times are determined by the SUT Fuses as shown
in
Table 7-9.
The Atmel
ter – CLKPR. This feature can be used to decrease power consumption when the requirement
for processing power is low. This can be used with all clock source options, and it will affect
the clock frequency of the CPU and all synchronous peripherals. clk
clk
When switching between prescaler settings, the system clock prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than either the
clock frequency corresponding to the previous setting or the clock frequency corresponding to
the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the
state of the prescaler, even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before
the new clock frequency is active. In this interval, twp active clock edges are produced. Here,
T1 is the previous clock period, and T2 is the period corresponding to the new prescaler
setting.
SUT1..0
Table 7-9 on page
FLASH
00
01
10
11
are divided by a factor as shown in
®
ATtiny24/44/84 system clock can be divided by setting the Clock Prescaler Regis-
Power-down and Power-save
Start-up Times for the 128kHz Internal Oscillator
Start-up Time from
31.
6CK
6CK
6CK
Atmel ATtiny24/44/84 [Preliminary]
Table 7-10 on page
Additional Delay from
Reserved
14CK + 64ms
14CK + 4ms
Reset
14CK
33.
I/O
BOD enabled
Fast rising power
Slowly rising power
, clk
Recommended Usage
ADC
, clk
CPU
, and
31
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