ATmega48 Automotive Atmel Corporation, ATmega48 Automotive Datasheet - Page 101
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ATmega48 Automotive
Manufacturer Part Number
ATmega48 Automotive
Description
Manufacturer
Atmel Corporation
Specifications of ATmega48 Automotive
Flash (kbytes)
4 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
256
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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14.7.1
14.7.2
14.7.3
7701E–AVR–02/11
Force Output Compare
Compare Match Blocking by TCNT1 Write
Using the Output Compare Unit
The OCR1x register is double buffered when using any of the twelve pulse width modulation
(PWM) modes. For the normal and clear timer on compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCR1x
compare register to either top or bottom of the counting sequence. The synchronization pre-
vents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output
glitch-free.
The OCR1x register access may seem complex, but this is not the case. When the double
buffering is enabled, the CPU has access to the OCR1x buffer register, and if double buffering
is disabled the CPU will access the OCR1x directly. The content of the OCR1x (buffer or com-
pare) register is changed only by a write operation (the timer/counter does not update this
register automatically as it does for the TCNT1 and ICR1 registers). Therefore, OCR1x is not
read via the high byte temporary register (TEMP). However, it is a good practice to read the
low byte first, as when accessing other 16-bit registers. Writing the OCR1x registers must be
done via the TEMP register because the compare of all 16 bits is done continuously. The high
byte (OCR1xH) has to be written first. When the high byte I/O location is written by the CPU,
the TEMP register will be updated by the value written. Then when the low byte (OCR1xL) is
written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the
OCR1x buffer or the OCR1x compare register in the same system clock cycle.
For more information of how to access the 16-bit registers, refer to
ters” on page
In non-PWM waveform generation modes, the match output of the comparator can be forced
by writing a logical one to the Force Output Compare (1x) bit. Forcing compare match will not
set the OCF1x flag or reload/clear the timer, but the OC1x pin will be updated as if a real com-
pare match had occurred (the COM11:0 bit settings define whether the OC1x pin is set,
cleared or toggled).
All CPU writes to the TCNT1 Register will block any compare match that occurs in the next
timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized
to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is
enabled.
Because writing TCNT1 in any mode of operation will block all compare matches for one timer
clock cycle, there are risks involved in changing TCNT1 when using any of the output compare
channels, independent of whether the timer/counter is running or not. If the value written to
TCNT1 equals the OCR1x value, the compare match will be missed, resulting in incorrect
waveform generation. Do not write the TCNT1 equal to top in PWM modes with variable top
values. The compare match for the top will be ignored, and the counter will continue to
0xFFFF. Similarly, do not write the TCNT1 value equal to bottom when the counter is
down-counting.
The setup of the OC1x should be performed before setting the data direction register for the
port pin to output. The easiest way of setting the OC1x value is to use the force output com-
pare (1x) strobe bits in normal mode. The OC1x register keeps its value even when changing
between waveform generation modes.
94.
Atmel ATtiny24/44/84 [Preliminary]
“Accessing 16-bit Regis-
101
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