ATmega48 Atmel Corporation, ATmega48 Datasheet - Page 218

• Manufacturer Part Number: ATmega48
• Manufacturer: Atmel Corporation

Specifications of ATmega48

• Flash (kbytes): 4 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 24
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 256
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.6
Figure 22-10. Interfacing the application to the TWI in a typical transmission.
2545T–AVR–05/11
Using the TWI
writes to TWCR to
TWI bus
transmission of
1. Application
START condition sent
Status code indicates
START
initiate
2. TWINT set.
START
TWDR, and loads appropriate control
3. Check TWSR to see if START was
signals into TWCR, makin sure that
sent. Application loads SLA+W into
The TWINT Flag is set in the following situations:
• After the TWI has transmitted a START/REPEATED START condition
• After the TWI has transmitted SLA+R/W
• After the TWI has transmitted an address byte
• After the TWI has lost arbitration
• After the TWI has been addressed by own slave address or general call
• After the TWI has received a data byte
• After a STOP or REPEATED START has been received while still addressed as a Slave
• When a bus error has occurred due to an illegal START or STOP condition
The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like
reception of a byte or transmission of a START condition. Because the TWI is interrupt-based,
the application software is free to carry on other operations during a TWI byte transfer. Note that
the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in
SREG allow the application to decide whether or not assertion of the TWINT Flag should gener-
ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in
order to detect actions on the TWI bus.
When the TWINT Flag is asserted, the TWI has finished an operation and awaits application
response. In this case, the TWI Status Register (TWSR) contains a value indicating the current
state of the TWI bus. The application software can then decide how the TWI should behave in
the next TWI bus cycle by manipulating the TWCR and TWDR Registers.
Figure 22-10
this example, a Master wishes to transmit a single data byte to a Slave. This description is quite
abstract, a more detailed explanation follows later in this section. A simple code example imple-
menting the desired behavior is also presented.
1. The first step in a TWI transmission is to transmit a START condition. This is done by
and TWSTA is written to zero.
TWINT is written to one,
writing a specific value into TWCR, instructing the TWI hardware to transmit a START
SLA+W
is a simple example of how the application can interface to the TWI hardware. In
Status code indicates
SLA+W sent, ACK
4. TWINT set.
received
A
Application loads data into TWDR, and
5. Check TWSR to see if SLA+W was
loads appropriate control signals into
TWCR, making sure that TWINT is
sent and ACK received.
written to one
Data
data sent, ACK received
Status code indicates
6. TWINT set.
ATmega48/88/168
A
making sure that TWINT is written to one
7. Check TWSR to see if data was sent
Application loads appropriate control
signals to send STOP into TWCR,
STOP
and ACK received.
TWINT set
Indicates
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