ATmega2561R212 Atmel Corporation, ATmega2561R212 Datasheet - Page 305
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ATmega2561R212
Manufacturer Part Number
ATmega2561R212
Description
Manufacturer
Atmel Corporation
Specifications of ATmega2561R212
Flash (kbytes)
256 Kbytes
Max. Operating Frequency
16 MHz
Max I/o Pins
54
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
8
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
6
Frequency Band
700/800/900MHz
Max Data Rate (mb/s)
1
Antenna Diversity
No
External Pa Control
Yes
Power Output (dbm)
10
Receiver Sensitivity (dbm)
-110
Receive Current Consumption (ma)
9.0
Transmit Current Consumption (ma)
18 at 5dBm
Link Budget (dbm)
120
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28.4.3
28.4.4
28.4.5
28.5
28.5.1
2549N–AVR–05/11
Boundary-scan Chain
SAMPLE_PRELOAD; 0x2
AVR_RESET; 0xC
BYPASS; 0xF
Scanning the Digital Port Pins
The active states are:
•
•
Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the
input/output pins without affecting the system operation. However, the output latches are not
connected to the pins. The Boundary-scan Chain is selected as Data Register.
The active states are:
•
•
•
The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or
releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one bit
Reset Register is selected as Data Register. Note that the reset will be active as long as there is
a logic “one” in the Reset Chain. The output from this chain is not latched.
The active states are:
•
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
•
•
The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connection.
Figure 28-3 on page 306
function is disabled during Boundary-scan when the JTAG IC contains EXTEST or
SAMPLE_PRELOAD. The cell consists of a bi-directional pin cell that combines the three sig-
nals Output Control - OCxn, Output Data - ODxn, and Input Data - IDxn, into only a two-stage
Shift Register. The port and pin indexes are not used in the following description.
The Boundary-scan logic is not included in the figures in the datasheet.
shows a simple digital port pin as described in the section
ary-scan details from
307.
When no alternate port function is present, the Input Data - ID - corresponds to the PINxn Regis-
ter value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output
Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain
Shift-DR: The IDCODE scan chain is shifted by the TCK input
Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain
Shift-DR: The Boundary-scan Chain is shifted by the TCK input
Update-DR: Data from the Boundary-scan chain is applied to the output latches. However,
the output latches are not connected to the pins
Shift-DR: The Reset Register is shifted by the TCK input
Capture-DR: Loads a logic “0” into the Bypass Register
Shift-DR: The Bypass Register cell between TDI and TDO is shifted
Figure 28-3 on page 306
shows the Boundary-scan Cell for a bi-directional port pin. The pull-up
ATmega640/1280/1281/2560/2561
replaces the dashed box in
“I/O-Ports” on page
Figure 28-4 on page 307
Figure 28-4 on page
70. The Bound-
305
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