AT90PWM316 Atmel Corporation, AT90PWM316 Datasheet - Page 173

• Manufacturer Part Number: AT90PWM316
• Manufacturer: Atmel Corporation

Specifications of AT90PWM316

• Flash (kbytes): 16 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 1
• Pwm Channels: 12
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

16.26.2
16.26.3
16.26.4
16.26.5
7710F–AVR–09/11
PSC0 Interrupt Mask Register – PIM0
PSC1 Interrupt Mask Register – PIM1
PSC2 Interrupt Mask Register – PIM2
PSC0 Interrupt Flag Register – PIFR0
• Bit 2 – POMV2A2: Output Matrix Output A Ramp 2
This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 2
• Bit 1 – POMV2A1: Output Matrix Output A Ramp 1
This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 1
• Bit 0 – POMV2A0: Output Matrix Output A Ramp 0
This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 0
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
• Bit 5 – PSEIEn : PSC n Synchro Error Interrupt Enable
When this bit is set, the PSEIn bit (if set) generate an interrupt.
• Bit 4 – PEVEnB : PSC n External Event B Interrupt Enable
When this bit is set, an external event which can generates a capture from Retrigger/Fault block
B generates also an interrupt.
• Bit 3 – PEVEnA : PSC n External Event A Interrupt Enable
When this bit is set, an external event which can generates a capture from Retrigger/Fault block
A generates also an interrupt.
• Bit 0 – PEOPEn : PSC n End Of Cycle Interrupt Enable
When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle.
Bit
Read/Write
Initial Value
POAC0B
R
R
R
R
7
0
7
0
7
0
7
0
-
-
-
POAC0A
R
R
R
R
6
0
6
0
6
0
6
0
-
-
-
PSEIE0
PSEIE1
PSEIE2
PSEI0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
PEVE0B
PEVE1B
PEVE2B
PEV0B
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
PEVE0A
PEVE1A
PEVE2A
PEV0A
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
PRN01
AT90PWM216/316
R
R
R
R
2
0
2
0
2
0
2
0
-
-
-
PRN00
R
R
R
R
1
0
1
0
1
0
1
0
-
-
-
PEOPE0
PEOPE1
PEOPE2
PEOP2
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
PIFR0
PIM0
PIM1
PIM2
173