AT90CAN64 Automotive Atmel Corporation, AT90CAN64 Automotive Datasheet - Page 121
AT90CAN64 Automotive
Manufacturer Part Number
AT90CAN64 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(431 pages)
2.AT90CAN128_AUTOMOTIVE.pdf
(16 pages)
3.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
Specifications of AT90CAN64 Automotive
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Can
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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15.3
15.3.1
7701E–AVR–02/11
Register Description
GTCCR – General Timer/Counter Control Register
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the
system clock frequency (f
uses sampling, the maximum frequency of an external clock it can detect is half the sampling
frequency (Nyquist sampling theorem). However, due to variation of the system clock fre-
quency and duty cycle caused by oscillator source (crystal, resonator, and capacitor)
tolerances, it is recommended that the maximum frequency of an external clock source is less
than f
An external clock source can not be prescaled.
Figure 15-2. Prescaler for Timer/Counter0
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to logical one activates the timer/counter synchronization mode. In this
mode, the value that is written to the PSR10 bit is kept, hence keeping the prescaler reset sig-
nal asserted. This ensures that the timer/counter is halted and can be configured without the
risk of advancing during configuration. When the TSM bit is written to logical zero, the PSR10
bit is cleared by hardware, and the timer/counter starts counting.
• Bit 0 – PSR10: Prescaler 0 Reset Timer/Counter n
When this bit is set to one, the timer/counter n prescaler will be reset. This bit is normally
cleared immediately by hardware, except if the TSM bit is set.
Bit
0x23 (0x43)
Read/Write
Initial Value
clk_I/O
1. The synchronization logic on the input pins (
/2.5.
PSR10
clk
T0
I/O
TSM
R/W
7
0
Synchronization
ExtClk
R
6
–
0
Atmel ATtiny24/44/84 [Preliminary]
< f
Clear
clk_I/O
R
5
–
0
/2) given a 50/50 duty cycle. Because the edge detector
R
4
–
0
T0)
R
3
–
0
is shown in
R
2
–
0
clk
Figure 15-1 on page
T0
R
1
–
0
PSR10
R/W
0
0
120.
GTCCR
121
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