AT90CAN64 Automotive Atmel Corporation, AT90CAN64 Automotive Datasheet - Page 113
AT90CAN64 Automotive
Manufacturer Part Number
AT90CAN64 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(431 pages)
2.AT90CAN128_AUTOMOTIVE.pdf
(16 pages)
3.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
Specifications of AT90CAN64 Automotive
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Can
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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14.11 Register Description
14.11.1
7701E–AVR–02/11
TCCR1A – Timer/Counter1 Control Register A
• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
The COM1A1:0 and COM1B1:0 control the output compare pins' (OC1A and OC1B, respec-
tively) behavior. If one or both of the COM1A1:0 bits are written to logical one, the OC1A
output overrides the normal port functionality of the I/O pin it is connected to. If one or both of
the COM1B1:0 bit are written to logical one, the OC1B output overrides the normal port func-
tionality of the I/O pin it is connected to. However, note that the data direction register (DDR)
bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver.
When OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent
on the WGM13:0 bit settings.
when the WGM13:0 bits are set to a normal or CTC mode (non-PWM).
Table 14-1.
Table 14-2 on page 113
to the fast PWM mode.
Table 14-2.
Note:
Bit
0x2F (0x4F)
Read/Write
Initial Value
COM1A1/COM1B1
COM1A1/COM1B1
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
0
0
1
1
0
0
1
1
this case the compare match is ignored, but the set or clear is done at BOTTOM. See
PWM Mode” on page 104
COM1A1
Compare Output Mode, non-PWM
Compare Output Mode, Fast PWM
R/W
7
0
COM1A0
COM1A0/COM1B0
COM1A0/COM1B0
shows the COM1x1:0 bit functionality when the WGM13:0 bits are set
R/W
6
0
Atmel ATtiny24/44/84 [Preliminary]
Table 14-1 on page 113
0
1
0
1
0
1
0
1
COM1B1
R/W
for more details.
5
0
COM1B0
R/W
4
0
Description
Normal port operation, OC1A/OC1B disconnected.
Toggle OC1A/OC1B on Compare Match.
Clear OC1A/OC1B on Compare Match (Set output to
low level).
Set OC1A/OC1B on Compare Match (Set output to
high level).
Description
Normal port operation, OC1A/OC1B disconnected.
WGM13=0: Normal port operation, OC1A/OC1B
disconnected.
WGM13=1: Toggle OC1A on Compare Match, OC1B
reserved.
Clear OC1A/OC1B on Compare Match, set
OC1A/OC1B at BOTTOM (non-inverting mode)
Set OC1A/OC1B on Compare Match, clear
OC1A/OC1B at BOTTOM (inverting mode)
(1)
R
3
–
0
shows the COM1x1:0 bit functionality
R
2
0
–
WGM11
R/W
1
0
WGM10
R/W
0
0
TCCR1A
“Fast
113
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