AT90CAN32 Atmel Corporation, AT90CAN32 Datasheet - Page 93
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AT90CAN32
Manufacturer Part Number
AT90CAN32
Description
Manufacturer
Atmel Corporation
Specifications of AT90CAN32
Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Can
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10. External Interrupts
10.1
10.1.1
7679H–CAN–08/08
External Interrupt Register Description
Asynchronous External Interrupt Control Register A – EICRA
The External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts
will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of gen-
erating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or
a low level. This is set up as indicated in the specification for the External Interrupt Control Reg-
isters – EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is
configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that
recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock,
described in
edge interrupt on INT3:0 are detected asynchronously. This implies that these interrupts can be
used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in
all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. This makes the MCU less sensitive to
noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the
Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the Watchdog Oscilla-
tor is voltage dependent as shown in the
will wake up if the input has the required level during this sampling or if it is held until the end of
the start-up time. The start-up time is defined by the SUT fuses as described in
on page
the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The
required level must be held long enough for the MCU to complete the wake up to trigger the level
interrupt.
• Bits 7..0 – ISC31, ISC30 – ISC01, ISC00: Asynchronous External Interrupt 3 - 0 Sense
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in
nously. Pulses on INT3:0 pins wider than the minimum pulse width given in
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an inter-
rupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur.
Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the
EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be
cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the
interrupt is re-enabled.
Bit
Read/Write
Initial Value
Control Bits
37. If the level is sampled twice by the Watchdog Oscillator clock but disappears before
“Clock Systems and their Distribution” on page
ISC31
R/W
7
0
ISC30
R/W
6
0
ISC21
R/W
5
0
Table
ISC20
R/W
4
0
“Electrical Characteristics (1)” on page
10-1. Edges on INT3..INT0 are registered asynchro-
ISC11
R/W
3
0
ISC10
R/W
2
0
AT90CAN32/64/128
37. Low level interrupts and the
ISC01
R/W
1
0
ISC00
R/W
0
0
Table 10-2
“System Clock”
EICRA
365. The MCU
will
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