AT90CAN32 Atmel Corporation, AT90CAN32 Datasheet - Page 111
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AT90CAN32
Manufacturer Part Number
AT90CAN32
Description
Manufacturer
Atmel Corporation
Specifications of AT90CAN32
Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Can
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Manufacturer
Quantity
Price
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12.9.2
7679H–CAN–08/08
Timer/Counter0 Register – TCNT0
Note:
Table 12-4
rect PWM mode.
Table 12-4.
Note:
• Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 12-5.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a compare match between TCNT0 and the OCR0A Register.
Bit
Read/Write
Initial Value
CS02
COM0A1
0
0
0
0
1
1
1
1
0
0
1
1
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
CS01
pare match is ignored, but the set or clear is done at TOP. See
for more details.
pare match is ignored, but the set or clear is done at TOP. See
page 107
shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase cor-
0
0
1
1
0
0
1
1
Compare Output Mode, Phase Correct PWM Mode
Clock Select Bit Description
R/W
7
0
COM0A0
CS00
for more details.
0
1
0
1
0
1
0
1
0
1
0
1
R/W
6
0
Description
No clock source (Timer/Counter stopped)
clk
clk
clk
clk
clk
External clock source on T0 pin. Clock on falling edge.
External clock source on T0 pin. Clock on rising edge.
Description
Normal port operation, OC0A disconnected.
Reserved
Clear OC0A on compare match when up-counting.
Set OC0A on compare match when downcounting.
Set OC0A on compare match when up-counting.
Clear OC0A on compare match when downcounting.
I/O
I/O
I/O
I/O
I/O
R/W
5
0
/(No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
R/W
4
0
TCNT0[7:0]
R/W
3
0
R/W
2
0
AT90CAN32/64/128
R/W
1
0
(1)
“Fast PWM Mode” on page 105
“Phase Correct PWM Mode” on
R/W
0
0
TCNT0
111
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