AT89LP51RC2 Atmel Corporation, AT89LP51RC2 Datasheet - Page 18

• Manufacturer Part Number: AT89LP51RC2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RC2

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 1.375
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

3.3.2
18
AT89LP51RB2/RC2/IC2 Preliminary
External Data Memory Interface
The AT89LP51RB2/RC2/IC2 uses the standard 8051 external data memory interface with the
upper address on Port 2, the lower address and data in/out multiplexed on Port 0, and the ALE,
RD and WR strobes. The interface may be used in two different configurations depending on
which type of MOVX instruction is used to access XDATA.
Figure 3-7
a 16-bit linear address. Port 0 serves as a multiplexed address/data bus to the RAM. The
Address Latch Enable strobe (ALE) is used to latch the lower address byte into an external reg-
ister so that Port 0 can be freed for data input/output. Port 2 provides the upper address byte
throughout the operation. The MOVX @DPTR instructions use Linear Address mode.
Figure 3-7.
Figure 3-8
an 8-bit paged address. Port 0 serves as a multiplexed address/data bus to the RAM. The ALE
strobe is used to latch the address byte into an external register so that Port 0 can be freed for
data input/output. The Port 2 I/O lines (or other ports) can provide control lines to page the mem-
ory; however, this operation is not handled automatically by hardware. The software application
must change the Port 2 register when appropriate to access different pages. The MOVX @Ri
instructions use Paged Address mode.
Figure 3-8.
Note that prior to using the external memory interface, WR (P3.6) and RD (P3.7) must be config-
ured as outputs. See
automatically to push-pull output mode when outputting address or data and P0 is automatically
tristated when inputting data regardless of the port configuration. The Port 0 configuration will
determine the idle state of Port 0 when not accessing the external memory.
shows a hardware configuration for accessing 256-byte blocks of external RAM using
shows a hardware configuration for accessing up to 64K bytes of external RAM using
External Data Memory 16-bit Linear Address Mode
External Data Memory 8-bit Paged Address Mode
Section 12.1 “Port Configuration” on page
P1
P1
RD
WR
RD
WR
AT89LP
AT89LP
P3
P3
P2
ALE
ALE
P0
P2
P0
I/O
LATCH
LATCH
PAGE
BITS
DATA
DATA
EXTERNAL
EXTERNAL
WE
MEMORY
MEMORY
WE
ADDR
ADDR
DATA
DATA
69. P0 and P2 are configured
OE
OE
3722A–MICRO–10/11