AT83C5135 Atmel Corporation, AT83C5135 Datasheet - Page 15
AT83C5135
Manufacturer Part Number
AT83C5135
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT83C5134.pdf
(166 pages)
Specifications of AT83C5135
Max. Operating Frequency
32 MHz
Cpu
8051-12C
Max I/o Pins
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
1
Sram (kbytes)
1.25
Eeprom (bytes)
512
Operating Voltage (vcc)
2.7 to 3.6
Timers
4
Mask Rom (kbytes)
16
Watchdog
Yes
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6.3.2
6.3.3
7683C–USB–11/07
PLL Programming
Divider Values
Figure 6-4.
The typical values are: R = 560 Ω, C1 = 820 pf, C2 = 150 pF.
The PLL is programmed using the flow shown in Figure 6-5. As soon as clock generation is
enabled user must wait until the lock indicator is set to ensure the clock output is stable.
Figure 6-5.
To generate a 48 MHz clock using the PLL, the divider values have to be configured following
the oscillator frequency. The typical divider values are shown in
Table 6-1.
Oscillator Frequency
12 MHz
16 MHz
18 MHz
20 MHz
24 MHz
3 MHz
6 MHz
8 MHz
PLL Filter Connection
PLL Programming Flow
Typical Divider Values
PLLF
R+1
16
12
Configure Dividers
8
6
4
3
8
2
Programming
PLL Locked?
N3:0 = xxxxb
R3:0 = xxxxb
LOCK = 1?
Enable PLL
PLLEN = 1
PLL
VSS
R
C1
VSS
N+1
1
1
1
1
1
3
5
1
C2
AT83C5134/35/36
Table
6-1.
PLLDIV
B4h
F0h
70h
50h
30h
20h
72h
10h
15
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