AT83C5135 Atmel Corporation, AT83C5135 Datasheet - Page 115
AT83C5135
Manufacturer Part Number
AT83C5135
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT83C5134.pdf
(166 pages)
Specifications of AT83C5135
Max. Operating Frequency
32 MHz
Cpu
8051-12C
Max I/o Pins
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
1
Sram (kbytes)
1.25
Eeprom (bytes)
512
Operating Voltage (vcc)
2.7 to 3.6
Timers
4
Mask Rom (kbytes)
16
Watchdog
Yes
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21.8.2
7683C–USB–11/07
Resume
The stop of the 48 MHz clock from the PLL should be done in the following order:
When the USB controller is in Suspend state, the Resume detection is active even if all the
clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit is set by
hardware when a non-idle state occurs on the USB bus. This triggers an interrupt if enabled.
This interrupt wakes up the CPU from its Idle or Power-down state and the interrupt function is
then executed. The firmware will first enable the 48 MHz generation and then reset to 0 the
SUSPCLK bit in the USBCON register if needed.
The firmware has to clear the SPINT bit in the USBINT register before any other USB operation
in order to wake up the USB controller from its Suspend mode.
The USB controller is then re-activated.
Figure 21-11. Example of a Suspend/Resume Management
1. Clear suspend interrupt bit in USBINT (required to allow the USB pads to enter power
2. Enable USB resume interrupt.
3. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUSPCLK bit
4. Disable the PLL by clearing the PLLEN bit in the PLLCON register.
5. Make the CPU core enter power down mode by setting PDOWN bit in PCON.
down mode).
in the USBCON register.
Detection of a SUSPEND State
Detection of a RESUME State
WUPCPU
SPINT
microcontroller in Power-down
Clear WUPCPU Bit
USB Controller Init
Clear SUSPCLK
Set SUSPCLK
Clear SPINT
Disable PLL
Enable PLL
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