AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 85
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AT32UC3L0256
Manufacturer Part Number
AT32UC3L0256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3L0128.pdf
(85 pages)
4.AT32UC3L0128.pdf
(852 pages)
Specifications of AT32UC3L0256
Flash (kbytes)
256 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
4
Lin
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3L0256-D3HR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3L0256-H
Manufacturer:
ATMEL
Quantity:
270
Part Number:
AT32UC3L0256-H
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
32002F–03/2010
Instruction
add r5, r0
sub r5, r5
ssrf AVR32_SREG_C
ssrf AVR32_SREG_GM
max r6, r1, r0
mul r5, r1
mac r5, r1
mac r3, r1
mac r3, r1
macs.d r2, r1, r2
mulwh.d r6, r5, r1:t
st.w IRAM[0], r6
divs r4, r5, r6
ld.w r8, IRAM++
satadd.w r4, r8, r9
ld.w r4, IRAM[4]
add r4, r4
ld.w r5, IRAM[8]
ld.w r6, IRAM[12]
ldm IRAM++, r5, r6, r7, r8
mfsr r8, AVR32_SREG
cbr r8, 0
mtsr AVR32_SREG, r8
st.w IRAM[0], r5
st.w IRAM[4], r6
nop
ld.w r5, HSB[0]
ld.w r6, HSB[4]
st.w HSB[8], r6
add r5, r6
and r7, r8
st.w HSB[8], r6
st.w HSB[12], r7
st.w HSB[16], r8
add r5, r6
• All instructions are executed in the precise sequence shown below
Cycles
1
1
1
3
1
1
1
2
1
4
1
1
35
2
1
1
1
1
1
5
1
1
3
1
1
1
2
2
1
1
1
2
1
1
1
48 bit result calculated and written back in 1 cycle
Load with postincrement takes two cycles
Loads from IRAM can be adjacent without any stalling
Stores to IRAM can be adjacent without any stalling
Reading from memories on the bus takes 2 cycles
HSB store done in background if 2 next insn is not mem access
Description
SSRF to bits 31-16 takes 3 cycles
1 cycle since r5 is already in the accumulator cache
2 cycles since r3 is not in the accumulator cache
1 cycle since r3 is not in the accumulator cache
4 cycles since register pair r3:r2 is not in the accumulator cache
No data hazard after loads from IRAM
ldm from IRAM takes 1+n= 5 cycles when loading 4 registers
mtsr to SREG takes 3 cycles, 1 cycle required for other sysregs
nop takes 1 cycle
HSB bus reads are not pipelined, each read takes 2 cycles
Nonmem insn scheduled after HSB store to avoid stall
Nonmem insn scheduled after HSB store to avoid stall
First of consecutive HSB stores requires extra cycle to start
Consecutive HSB stores are pipelined.
Consecutive HSB stores are pipelined.
Consecutive HSB stores followed by 1 nonmem insn do not stall
AVR32
85