AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 63
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AT32UC3L0256
Manufacturer Part Number
AT32UC3L0256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3L0128.pdf
(85 pages)
4.AT32UC3L0128.pdf
(852 pages)
Specifications of AT32UC3L0256
Flash (kbytes)
256 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
4
Lin
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3L0256-D3HR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3L0256-H
Manufacturer:
ATMEL
Quantity:
270
Part Number:
AT32UC3L0256-H
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
6.4.3
32002F–03/2010
EX stage local bus interface
access to the RAMs when the current owner voluntarily releases the RAMs, or after the
SPL/CPL timeout period, whichever comes first.
If the CPU wins arbitration for the RAMs, the CPU is guaranteed to own the RAM for the period
specified by the COP field in CPUCR. Any slave request will be left pending during this period,
even if the CPU is not using the RAMs.
The following state diagram shows the states in arbitration for the RAM.
Figure 6-2.
The state transitions are as follows:
Any CPU access to the the LOCAL section is completed in a single clock cycle, both for reads
and writes. Transfers on this bus can not be stalled. The CPU will never be stalled due to an
access to the LOCAL section. Accesses to this section is performed using regular load-store
instructions such as for example ldswp.w, ld.w, ld.ub, st.w, stswp.w, ldm or stm.
Which devices are mapped in the LOCAL section, and their memory maps, is device-specific.
The LOCAL interface must be enabled by the user by programming the LOCEN bit in CPUCR.
Accesses to LOCAL memory addresses without first enabling the section will result in a BUS
ERROR exception.
If the MPU is enabled, accesses to LOCAL will be subject to permission checking.
To ensure maximum transfer speed and cycle determinism, any slaves being addressed by the
CPU on the local bus must be able to receive and transmit data on the bus at CPU clock speeds.
The consequences of this may vary between different slave devices, but for some slave devices
it may imply that the slaves have to run at the CPU clock frequency when local bus transfers are
1: CPU_wants_to_perform_mem_access
2: CPU_access_complete && (been_in_state > CPUCR[COP])
3: (been_in_state > CPUCR[COP]) && slave_wants_to_perform_mem_access &&
(slave_been_pending > CPUCR[SPL])
4: CPU_wants_to_perform_mem_access && (CPU_been_pending > CPUCR[CPL])
5: slave_wants_to_perform_mem_access && !CPU_wants_to_perform_mem_access
6: slave_access_complete
CPU owns the RAM
Arbitration between CPU and slave interface for RAMs.
1
2
RAM is free
3
4
6
Slave I/F owns the RAM
5
AVR32
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