AT32UC3L016 Atmel Corporation, AT32UC3L016 Datasheet - Page 41

• Manufacturer Part Number: AT32UC3L016
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L016

• Flash (kbytes): 16 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.2.2.6
32000D–04/2011
TLB Accessed Register HI / LO - TLBARHI / TLBARLO
Table 5-4.
The TLBARHI and TLBARLO register form one 64-bit register with 64 1-bit fields. Each of these
fields contain the Accessed bit for the corresponding TLB entry. The I bit in TLBEHI determines
whether the ITLB or DTLB Accessed bits are read. The Accessed bit is 0 if the page has been
accessed, and 1 if it has not been accessed. Bit 31-0 in TLBARLO correspond to TLB entry 0-
31, bit 31-0 in TLBARHI correspond to TLB entry 32-63. If the TLB implementation contains less
than 64 entries then nonimplemented entries are read as 0.
Note: The contents of TLBARHI/TLBARLO are reversed to let the Count Leading Zero (CLZ)
instruction be used directly on the contents of the registers. E.g. if CLZ returns the value four on
the contents of TLBARLO, then item four is the first unused item in the TLB.
M
0
1
• ILA - Instruction TLB Lockdown Amount. Specified the number of locked down ITLB entries.
• DRP - Data TLB Replacement Pointer. Points to the DTLB entry to overwrite when a new
• DLA - Data TLB Lockdown Amount. Specified the number of locked down DTLB or UTLB
• S - Segmentation Enable. If set, the segmented memory model is used in the translation
• N - Not Found. Set if the entry searched for by the TLB Search instruction (tlbs) was not
• I - Invalidate. Writing this bit to one invalidates all TLB entries. The bit is automatically cleared
• M - Mode. Selects whether the shared virtual memory mode or the private virtual memory
• E - Enable. If set, the MMU translation is enabled. If cleared, the MMU translation is disabled
entries in the ITLB. It is IMPLEMENTATION DEFINED whether to use fewer entries.
Impementations with a single unified TLB does not use the IRP field.
All ITLB entries from entry 0 to entry (ILA-1) are locked down. If ILA equals zero, no entries
are locked down. Implementations with a single unified TLB does not use the ILA field.
entry is loaded by the tlbw instruction. The DRP field may be updated automatically in an
IMPLEMENTATION DEFINED manner in order to optimize the replacement algorithm. The
DRP field can also be written by software, allowing the exception routine to implement a
replacement algorithm in software. The DRP field is 6 bits wide, allowing a maximum of 64
entries in the DTLB. It is IMPLEMENTATION DEFINED whether to use fewer entries.
Implementations with a single unified TLB use the DRP field to point into the unified TLB.
entries. All DTLB entries from entry 0 to entry (DLA-1) are locked down. If DLA equals zero,
no entries are locked down.
process. If cleared, the memory is regarded as unsegmented. The S bit is set after reset.
found in the TLB.
by the MMU when the invalidate operation is finished.
mode should be used. The M bit determines how the TLB address comparison should be
performed, see
and the physical address is identical to the virtual address. Access permissions are not
checked and no MMU-related exceptions are issued if the MMU is disabled. If the MMU is
disabled, the segmented memory model is used.
MMU mode implied by the M bit
Table 5-4 on page
Mode
Private Virtual Memory
Shared Virtual Memory
41.
AVR32
41