AT32UC3C1256C Atmel Corporation, AT32UC3C1256C Datasheet - Page 7
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AT32UC3C1256C
Manufacturer Part Number
AT32UC3C1256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C1256C
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C1256C-AUR
Manufacturer:
LORLIN
Quantity:
1 000
Company:
Part Number:
AT32UC3C1256C-AUT
Manufacturer:
ATMEL
Quantity:
1 001
2. Programming Model
2.1
2.2
2.2.1
2.2.2
2.2.3
2.3
32002F–03/2010
Architectural compatibility
Implementation options
Register file configuration
Memory protection
Java support
Floating-Point Hardware
This chapter describes the programming model and the set of registers accessible to the user. It
also describes the implementation options in AVR32UC.
AVR32UC is fully compatible with the Atmel AVR32A architecture. AVR32UC devices imple-
menting both revision 2 and revision 3 of the AVR32 Architecture exist. Refer to the device
datasheet or the device’s CONFIG0 register to determine which architecture revision the device
implements.
Architecture revision 3 is fully backwards compatible with revision 2, and additionally
implements:
AVR32UC optionally supports an MPU as specified by the AVR32 architecture.
AVR32UC does not implement Java hardware acceleration.
AVR32UC optionally supports Floating-Point Hardware implemented as coprocessor
instructions.
The AVR32A architecture dictates a specific register file implementation, reproduced below.
Secure state context and secure state system registers are only available in devices implement-
ing revision 3 of the AVR32 architecture.
• Secure state with associated programming model
• The automatic clearing of COUNT on COMPARE match is now optional and disabled by
setting the NOCOMPRES bit in CPUCR.
AVR32
7