AT32UC3C1256C Atmel Corporation, AT32UC3C1256C Datasheet - Page 4
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AT32UC3C1256C
Manufacturer Part Number
AT32UC3C1256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C1256C
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C1256C-AUR
Manufacturer:
LORLIN
Quantity:
1 000
Company:
Part Number:
AT32UC3C1256C-AUT
Manufacturer:
ATMEL
Quantity:
1 001
1.7
32002F–03/2010
The AVR32UC architecture
Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These
registers are pushed regardless of the priority level of the pending interrupt. The return address
and status register are also automatically pushed to stack. The interrupt handler can therefore
use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are
restored, and execution continues at the return address stored popped from stack.
The stack is also used to store the status register and return address for exceptions and scall.
Executing the rete or rets instruction at the completion of an exception or system call will pop
this status register and continue execution at the popped return address.
The first implementation of the AVR32A architecture is called AVR32UC. This implementation
targets low- and medium-performance applications, and provides an optional, advanced OCD
system, no data or instruction caches, and an optional Memory Protection Unit (MPU). Java
acceleration is not implemented.
AVR32UC provides three memory interfaces, one High Speed Bus (HSB) master for instruction
fetch, one HSB bus master for data access, and one HSB slave interface allowing other bus
masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the CPU
allows fast access to the RAMs, reduces latency and guarantees deterministic timing. Also,
power consumption is reduced by not needing a full HSB bus access for memory accesses. A
dedicated data RAM interface is provided for communicating with the internal data RAMs.
If an optional MPU is present, all memory accesses are checked for privilege violations. If an
access is attempted to an illegal memory address, the access is aborted and an exception is
taken.
The following figure displays the contents of AVR32UC:
AVR32
4